Bang-bang Phase-locked Loops Research Articles

Transient analysis of bang–bang phase locked loops for phase step inputs

Regarding to the nonlinear nature of the bang---bang phase-locked loops (BBPLLs), its transient analysis is very complicated. In this paper, new equations are proposed, expressing transient behavior of the BBPLLs with first order filter in response to phase step input. This approach gives new insights into the transient behavior of the BBPLLs. Approximating transient response by a reasonable specific waveform; the loop transient time characteristics such as locking time, peak time, rise time and over shoot are derived with acceptable accuracy. The validity of the resulted equations is verified through simulations using MATLAB SIMULINK. Simulation results show the high accuracy of the proposed equations for BBPLLs transient behavior.

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter.

Spur reduction in bang-bang PLLs using programmable bit-stream

All-digital bang-bang phase-locked loops (PLLs) are prone to spurious output tones. In this reported work, a programmable bit-sequence is generated and used as a time-mode dithering signal. The bit-stream can be programmed to emulate the required order of a ΣΔ modulator operating in the time-domain without need for any hardware change. This method leads to a low-cost, compact, low-power and versatile phase noise-shaping scheme.

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Bang-bang phase-locked loops are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear phase detector, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either nonaccumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief, we consider the case of accumulative digitally-controlled oscillator (DCO) jitter and derive an asymptotic closed-form expression for the BPD gain, which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal Laplace distribution.

Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear due to the hard nonlinearity introduced by the binary phase detector (BPD). This paper provides an exact statistical analysis of the steady-state timing jitter in a first-order BBPLL when the reference clock is subject to accumulative jitter. By elaborating on the analogy of viewing a first-order BBPLL as a single-integration delta modulator (DM) in the phase domain, we are able to relate hunting jitter and slew-rate limiting in a BBPLL to granular noise and slope overload in a DM. The stochastic timing-jitter behavior is modeled as a sign-dependent random walk, for which we obtain the asymptotic characteristic function and analytical expressions for the first four cumulants. These expressions are applied to the BBPLL to statistically analyze the static timing offset and the rms timing jitter, including the effect of a frequency offset. The analysis shows that the rms timing jitter is constant for small rms clock jitter and grows quadratically with large rms clock jitter, and that there exists an optimal bang-bang phase step for minimum rms timing jitter. Computing the kurtosis reveals the effect of the BPD nonlinearity: The timing jitter is largely non-Gaussian.

Noise Analysis and Minimization in Bang-Bang Digital PLLs

In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase detector and the frequency granularity of the digitally controlled oscillator (DCO) can give rise to undesired tones or peaking in the output spectrum. This work derives the maximum ratio between DCO resolution and jitter, which avoids limit cycles, in the case of dominant DCO noise over reference noise. Moreover, the output jitter is expressed in closed form as a function of the loop parameters and latency, revealing the existence of a minimum and suggesting an optimum design criterion. Finally, an estimation of the BBPLL output spectrum taking into account the quantization noise is provided.

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.

Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay

A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state flow diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated.

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

Due to the presence of a binary phase detector (BPD) in the loop, bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems. Since the BPD is usually also the only nonlinear element in the loop, in practical applications, BBPLLs are commonly analyzed by first linearizing the BPD and then using the traditional mathematical techniques for linear systems. To the author's knowledge, in the literature, the gain of the linearized BPD (K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bpd</sub> ) is determined neglecting the effect of the BBPLL dynamics on the effective jitter seen by the BPD. In this brief, we develop an approach to the determination of K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bpd</sub> which takes into consideration also this effect. The approach is based on modeling the dynamics of a BBPLL as a Markov chain. This approach gives new insights into the behavior of the BBPLL and leads to an expression for the Kbpd, which is more general than the one currently known in literature

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a lot of communications systems, in particular in the area of clock and data recovery. Although most of the BBPLLs implemented up to now use analog loop filters, the binary output of the phase detector naturally lends itself to a digital implementation. In this paper, the nonlinear dynamics of first- and second-order digital BBPLLs is analyzed from a design perspective. In particular, the effects of loop delays on the PLL performances are emphasized. Conditions for the existence of orbits (limit cycles) are derived, and the timing jitter performances are evaluated. Finally, useful expressions for the design and optimization of the PLL parameters for low jitter are given.

Corrections to "Analysis of a half-rate bang-bang phase-locked loop"

Corrections to "Analysis of a half-rate bang-bang phase-locked loop"