Bang-bang Phase-locked Loops Research Articles

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power XOR-based quadrupler for clocking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of −59.7 dBc, while the measured out-of-band noise is −140.7 dBc/Hz at a 10-MHz offset.

A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators

This paper describes an efficient way to reduce the quantization noise of delta-sigma fractional-N PLLs by using an injection-locked oscillator (ILO) in the feedback path. For further noise reduction, the use of cascaded ILOs is proposed. Behaving like a type-I high-order PLL, the cascaded ILOs effectively suppress the quantization noise like a high-order phase-domain low-pass filter (PDLPF). We show that the proposed ILO-based PDLPF significantly improves the out-of-band phase noise for wideband fractional-N PLLs as well as the in-band phase noise for fractional-N bang-bang PLLs (BBPLLs). Post-layout simulation results show that a ΔΣ fractional-N BBPLL with a 3-stage ILO can achieve the in-band noise reduction of 25 dB without having a nested PLL.

Fast-Switching Technique for Fractional-N Digital Bang-Bang PLL-Based Frequency Synthesizers

This brief proposes a novel fast-switching technique based on an asymmetrical tuning mechanism and a changeable convergence factor for fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital Bang-Bang (BB) phase-locked loops (PLLs). Advantage of the proposed technique in boosting speed of frequency-locking and calibration-gain convergence is clarified by a comprehensive analysis of the BB-PLL non-linear behavior. Simulated switching-time of the PLL models for use in wireless applications show significant improvement of the proposed technique over the conventional one.

A Digital PLL With Multitap LMS-Based Bandwidth Control

Automatic bandwidth control based on least-mean-square adaptive filters has been demonstrated to desensitize the loop gain of a phase-locked loop from process spreads, environmental variations and channel frequency. This work extends this concept to low-jitter designs that adopts aggressive out-of-band filtering, by introducing multi-tap adaptive filtering. The method requires no injection of a training sequence, potentially degrading phase noise, and it is particularly suitable for bang-bang PLLs whose loop bandwidth depends on input noise. A 3.7-to-4.1-GHz PLL prototype embedding a 16-tap adaptive filter for loop gain estimation demonstrates 150-kHz loop bandwidth over input noise and voltage supply variations, at 183-fs RMS integrated jitter and 5.3-mW power consumption.

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions.

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

This article presents a fractional-N frequency synthesizer architecture that is able to overcome the limitations of conventional bang-bang phase-locked loops. A digital frequencyerror recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional-N operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 μs. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional-N and integer-N modes, respectively. The worst-case in-band fractional spur is at -61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of -250.6 dB for the fractional-N channels.

Analysis of Frequency-Aid Technique for Fractional-N Digital BB-PLLs in Time-Domain

This brief make an original analysis of the frequency-aid technique using ternary phase detectors (TPDs) for fractional-N digital Bang-Bang (BB) phase-locked loops (PLLs). We prove that the minimum value of the TPD dead-zone to prevent a limit-cycle happening in the BB-PLL, in fact, can be reduced by a factor of 28 when using a novel mathematical expression, for a reference signal with -155 dB noise floor. Furthermore, we show that increasing the gain of the integral path tuning the digitally-controlled oscillator coarse bank does not guarantee a faster locking as typically believed. Finally, this brief proposes closed-form expressions for the TPD dead-zone and the gain of the additional proportional path to minimize the transient time.

A Robust BBPLL-Based 0.18-$\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 °C–175 °C Temperature Range

This paper presents a drift-resilient time-based resistive sensor interface in a 0.18- $\mu \text{m}$ CMOS technology. The interface is built around only two oscillators, a phase detector, a digital filter, and a digital-to-analog converter (DAC), resulting in a simple first-order Delta–Sigma design with a predictable transfer function. The highly digital approach not only results in a small area but also implies that only a few analog circuits are sensitive to drift. The holistic drift-resilience strategy implemented combines time-based chopping and voltage-controlled oscillator (VCO) tuning to remove the dc and low-frequency errors introduced by VCO nonidealities and drift. These techniques do not introduce a significant area and power overhead. Silicon measurements show that the proposed bang–bang phase-locked loop (BBPLL)-based sensor interface exhibits ppm-level gain drift and offset drift for the entire −40 °C–175 °C temperature range while using a single-temperature calibration scheme and no external accurate references nor components for this drift stability. The interface provides a 15-effective number of bits conversion for a 100-ms conversion time and consumes 3.41 mW of power and occupies only 0.23 mm2 of the active area.

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc.

A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation

This paper describes a low-power phase-domain receiver with single-bit phase-to-digital conversion by utilizing a divider-less bang-bang phase-locked loop (BBPLL). The BBPLL performs 1-bit oversampled noise-shaping demodulation as a secondary loop in the receiver, offering a flexible gain control as well as a simple baseband interface. A prototype 2.4-GHz receiver with an auxiliary 50-MHz BBPLL is implemented in 65-nm CMOS. In the RF loop, a dual-path LC voltage-controlled oscillator (VCO) with partitioned coarse tuning is designed to have a low gain constant over temperature variation. In the BBPLL, a dual-input ring VCO provides separate gain control and low-pass filtering for the demodulation path. The receiver performs 100-kb/s Gaussian Frequency Shift Keying (GFSK) demodulation with the sensitivity of -89 dBm and the power consumption of 3.7 mW from a 0.8-V supply in which 0.15 mW is consumed by the BBPLL.

A fast-locking bang-bang phase-locked loop with adaptive loop gain controller * * Project supported by the National Nature Science Foundation of China (Nos. 61331003, 61474108), the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (No. 2016ZX03001002).

This paper proposes a fast-locking bang-bang phase-locked loop (BBPLL). A novel adaptive loop gain controller (ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector (BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm2. Measured results show that the BBPLL operates at a frequency range from 0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1 μs @ 100 MHz frequency jump. The figure-of-merit of the fast-locking BBPLL is −334 dB.

A Background Calibration Technique to Control the Bandwidth of Digital PLLs

This paper presents a technique to regulate the bandwidth of digital phase-locked loops (PLLs), where a fully digital automatic control circuit, running in background, is used to desensitize loop gain from analog parameters. The method that is based on an adaptive least-mean-squares algorithm requires no injection of a training sequence, potentially degrading phase noise performance, and is suitable in particular for bang-bang PLLs, where the bandwidth depends on the input noise. The operating principle is first introduced and discussed with the help of an intuitive time-domain model, and the algorithm extension addressing the practical implementation issues associated with loop latency is then presented. The calibration circuit is embedded in a 65-nm CMOS digital PLL that achieves 400-fs integrated rms jitter with a power consumption of 4.5 mW. The algorithm enables digital programmability of loop bandwidth from 100 kHz to 2 MHz with an error below 1 dB between the theoretical and measured PLL noise transfer functions.

A Low-Jitter Full-Rate 25-Gb/s CDR for 100-Gb/s Optical Interconnects in 0.13-μm SiGe BiCMOS

ABSTRACTA low-jitter full-rate 25-Gb/s clock and data recovery (CDR) chip for 100-Gb/s optical interconnects is proposed. Fabricated in 0.13-μm SiGe BiCMOS technology, the chip is implemented in a third-order type-II bang-bang phase-locked loop (BBPLL) topology. To achieve optimal switching speed, all SiGe heterojunction bipolar transistors (HBTs) in high-speed blocks are biased at peak fT current density. Transistors are sized by carefully balancing speed versus power consumption. Emitter-coupled logic (ECL) and current-mode logic (CML) are employed in logic components. Compared with conventional spiral inductors, the employment of RF transmission lines in resonators of the VCO reduces the area of the VCO and, thus, the whole chip, without sacrificing the performance. The core circuits occupy an area of 0.48 mm2. The CDR recovers a clock with an rms jitter of 750 fs and a peak-to-peak jitter only of 3.46 ps.

Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps to answer long-standing questions on aspects of these circuits attributable a hard nonlinearity. A brief designer’s guide is included.

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f 2 and 1/f 3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.

Transient Analysis of Bang–Bang Phase-Locked Loops for Frequency Step Inputs

In this paper, an exact transient analysis of bang–bang PLLs (BBPLLs) as a nonlinear system, is presented. The proposed analysis considers the input step in frequency. The results contain all important times, the related VCO control voltage and output excess phase. We considered frequency steps in which BBPLL does not experience cycle slipping. We could obtain an expression for maximum frequency step size in which cycle slipping does not occur. To evaluate the proposed analysis, many simulations are performed using MATLAB SIMULINK where all show very high accuracy of the proposed equations.

Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs

In this paper, the multifaceted behavior of bang-bang digital phase-locked loops is explored. It is proved that a stochastic resonance phenomenon occurs at the balance between the quantization and intrinsic noise of the digitally controlled oscillator, which resides into the loop. How this condition maximizes the signal-to-noise performance is shown. The loop parameter value that yields stochastic resonance is provided in closed form.

Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters

Highly digital-oriented architectures for sensor interfaces are very interesting for their high energy efficiency, especially in smaller CMOS technologies which offer low-voltage design. This paper presents the analysis of a Bang-Bang Phase-Locked Loop Sensor-to-Digital Converter (BBPLL SDC). The highly digital-oriented BBPLL offers advantages such as the low chip area, excellent scalability towards smaller technologies, robustness towards process variations and low-voltage possibilities, making this architecture very interesting for energy-efficient applications. Theoretical analysis of the structure shows that the BBPLL SDC resembles a -modulator with first-order quantization noise shaping due to the frequency-to-phase conversion of the oscillators. Oscillator phase noise however plays an important role in the analysis and limits the SNR in practical implementations. To validate the theoretical analysis, a state-variable-based non-linear Matlab model has been developed, including non-idealities such as phase noise, non-linearity and mismatch. Based on practically achievable phase noise values of state of the art oscillators, simulations show that resolutions up to 110 dB can be achieved. An estimation of the power consumption of the oscillators, based on state of the art figures, results in energy-efficient designs beyond the state of the art with moderate resolutions of 40-80 dB SNR, while high resolutions of 80-110 dB demand higher power consumption in the oscillators, resulting in designs with lower energy efficiency, but still competitive with the current state of the art. A design strategy for both an energy-efficient and a high-performance BBPLL SDC is provided.

Comparing techniques for spur reduction in digital bang‐bang PLLs

Bang-bang phase-locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor.

Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems

Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indicating that the system is prone to be unstable. Stability analysis of the BPLLs is conducted to derive stability conditions, taking advantage of the radius of curvature technique to facilitate numerical calculations involved. It is shown that the stability conditions depend on the LF parameters, the loop delay, and the update time of the BPLLs.