Digital Bang-bang Phase-locked Loops Research Articles

A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors

This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a comparator-based bang-bang phase/frequency detector (PFD), and a digital loop filter (DLF). The PLL locks the DCO to a reference frequency, making its digital input a direct representation of the sensing coil inductance. To compensate for the coil inductance tolerances, the DCO's center frequency can be trimmed by a second capacitive DAC. This approach obviates the need for a reference coil. When combined with a 5-mm-diameter sensing coil located 500 μm from a metal target, the interface achieves a displacement resolution of 6.7 nm (rms) in a 3-kHz bandwidth. It consumes 200 μW from a 1.8-V power supply, which represents the best-reported tradeoff between power consumption, bandwidth, and resolution.

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM $_{T}$ of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its frequency acquisition time improves from 780 to 45 $\mu \text{s}$ with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC -based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of −104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times $ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm2 and consumes 40 mW.

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\mu$ s Settling Time for Multi-ISM-Band ULP Radios

This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively shorten the calibration time, while the split coarse-fine PLL loops with different loop bandwidths accelerate the loop settling speed. The employed ring VCO (RVCO) aids to extend the frequency tuning range and generate multi-phase outputs. Prototyped in 65-nm CMOS, the DPLL consumes 1.2–2.4 mW over a wide frequency locking range of 68.3% (1.3–2.65 GHz) and occupies a die area of 0.12 mm2. The settling time measures $8~\mu \text{s}$ at an 82-MHz initial frequency error.

Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang–Bang Digital PLL With Transport Delay Using Fokker–Planck Equations

In this paper, a second-order bang-bang digital phase-locked loop (BBPLL) with dominant random walk phase noise and transport delay is analyzed using Fokker-Plank equations. Explicit closed-form expressions are derived for the timing error probability distribution function, jitter variance, and power spectral density (psd). For the type-II BBPLL considered in this paper, the timing error distribution is shown to be Laplacian and not Gaussian distributed as previously assumed, while the derived psd is Lorentzian, which is consistent with earlier works. The analytical solutions are valid as long as the continuous-time approximation of the BBPLL dynamics is accurate as is the case for typical operating loop bandwidths. The accuracy of the derived expressions is validated via simulation.

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).

최적 루프 이득 제어에 의한 광대역 뱅뱅 디지털 위상 동기 루프 선형화 기법

본 논문은 광대역 특성의 뱅뱅 디지털 위상 동기 루프를 설계함에 있어 최적의 루프 이득 선정을 통한 실용적인 선형화 설계 기법을 제안한다. 기존의 이론적 파라미터 설계 기법을 광대역 클럭 발생기 회로에 적용함에 있어 한계점을 설명하고 실제 구현된 뱅뱅 디지털 위상 동기 루프 설계에 대해서 살펴보았다. 본 논문에서는 정수 어레이와 디더 이득은 크게 하되 비례 이득을 작게 설정하여 뱅뱅 디지털 위상 동기 루프의 리미티드 사이클 노이즈를 제거하였다. 제안된 설계 기법을 적용한 뱅뱅 디지털 위상 동기 루프는 기존의 구조에 비교하여 초소형, 저전력, 선형 특성 및 루프 대역폭 조절이 가능한 장점을 보이며, 성능의 우수성을 시뮬레이션을 통하여 검증하였다.<BR><BR>

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f 2 and 1/f 3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter.

Noise Analysis and Minimization in Bang-Bang Digital PLLs

In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase detector and the frequency granularity of the digitally controlled oscillator (DCO) can give rise to undesired tones or peaking in the output spectrum. This work derives the maximum ratio between DCO resolution and jitter, which avoids limit cycles, in the case of dominant DCO noise over reference noise. Moreover, the output jitter is expressed in closed form as a function of the loop parameters and latency, revealing the existence of a minimum and suggesting an optimum design criterion. Finally, an estimation of the BBPLL output spectrum taking into account the quantization noise is provided.

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.