Continuous-time Bandpass Sigma-delta Modulator Research Articles

A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer

We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-order single-loop continuous-time bandpass delta-sigma modulator (CT-BP- ΔΣM). The design is amenable to nanoscale CMOS and exploits a single self-biased pseudo-differential inverter with a positive feedback to replace conventional op-amps used in an integrator configuration. The modulator also uses a 5-bit asynchronous successive approximation register (ASAR) quantizer. With a 30 MHz bandwidth at 400 MS/s sampling rate and 100 MHz intermediate frequency (IF), the modulator achieves 61 dB dynamic range (DR) and 58 dB SNDR while consuming 2.5 mW from a 1V supply. The core area in 28 nm LP CMOS is 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 38.6 fJ/conv.-step figure of merit is achieved.

An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems.

This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.

A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS

A 1 GHz intermediate frequency, 16-element, 4-beam digital beamformer facilitates multi-in multi-out, 5G mobile, and other emerging communication standards. Digital beamforming has been limited by high power consumption, large die area, and the need for a large number of analog-to-digital converters (ADCs). The proposed digital beamformer addresses these issues by combining interleaved bit stream processing (IL-BSP) with power- and area-efficient continuous-time bandpass delta-sigma modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. The new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% with a power- and area-efficient three-stage nested $G_{m} - {C}$ op-amp and a passive summer. With an 11.2 dB array gain, the digital beamformer achieves a 58.5 dB signal to noise and distortion ratio and a 59.6 dB SNR over a 100 MHz bandwidth. Thanks to the accurate digitization and digital processing, the measured beam patterns of the four simultaneous beams are near ideal.

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.

High-speed continuous-time band pass ΔΣ modulator for class-S systems

A fully integrated continuous-time bandpass delta-sigma modulator (BPDSM) fabricated in a 0.25μm SiGe BiCMOS is presented. It consists of a two-stage second-order resonator, high-speed comparator, multi-feedback current digital-to-analog converter, and an output buffer. The input frequency can be tuned from 3.55 to 3.9GHz at a 9.5GHz fixed sampling clock frequency. This modulator dissipates 109mA from a 3.3V power supply. The peak signal-to-noise ratio (SNR) of the sine-wave input is 37.3dB in a 20MHz channel bandwidth, and the error vector magnitude (EVM) of a 64QAM long-term evolution (LTE) downlink signal is 5.94% with a 10.5dB peak-to-average-power ratio (PAPR).

LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency

This paper analyses the use of bandpass continuous-time ΣΔ modulators with widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The modulator architectures under study are based on a fourth-order loop filter - implemented with two LC-based resonators - and a finite-impulsive-response feedback loop in order to increase their flexibility and degrees of freedom. Several topologies are studied, considering three different cases for the embedded digital-to-analog converter, namely: return-to-zero, non-return-to-zero and raised-cosine waveform. In all cases, a notch-aware synthesis methodology is presented, which takes into account the dependency of the loop-filter coefficients on the notch frequency and compensates for the dynamic range degradation due to the variation of the notch. The synthesized modulators are compared in terms of their sensitivity to main circuit error mechanisms and the estimated power consumption over a notch-frequency tuning range of 0.1fs to 0.4fs. Time-domain behavioral and macromodel electrical simulations validate this approach, demonstrating the feasibility of the presented methodology and architectures for the efficient and robust digitization of radio-frequency signals with a scalable resolution and programmable signal bandwidth.

A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators

Excess loop delay is one of the most critical non-idealities of continuous-time delta---sigma modulators as it leads to degradation of the signal-to-noise-ratio or even instability. A comprehensive study of the impact of excess loop delay on tunable continuous-time bandpass delta---sigma modulators using RC-resonators is performed in this paper, both analytically and by simulations. Moreover, a detailed analysis of the conventional compensation techniques for single-band continuous-time bandpass modulators as well as their adaptability to tunable bandpass modulators is performed. The results indicate that only tuning of the scaling coefficients is suitable to compensate for excess loop delay in high-speed tunable bandpass modulators. Based on this result, an approach to the compensation of excess loop delay is proposed which maps the poles of the noise transfer function (NFT) to almost ideal and thus stable positions. Excess loop delay equal to one clock cycle may thus be compensated while the available tuning range of the center frequency depends on the order and the out-of-band-gain of the NFT. A prototype implemented on a printed circuit board proves the feasibility of the proposed approach.

A 2-bit, 3.1 GS/s, band-pass DSM receiver for active antenna systems

This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are −6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is −62.6 and −52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier.

A High Voltage Swing Dual-Band Bandpass $\Delta\Sigma$ Modulator for Mobile Base-Station

A fully integrated high voltage swing dual-band continuous-time bandpass delta-sigma modulator (CT BPDSM) with a high voltage swing and fabricated on a 0.25 μm SiGe BiCMOS is presented. The proposed CT BPDSM consists of a two-stage second-order resonator, a high speed comparator, multi-feedback current DACs, and a high voltage swing driver. The band selection is controlled using a capacitor bank, and fine frequency tuning is conducted by a varactor. At 883 and 955 MHz, the implemented BPDSM with a high voltage swing shows a peak SNR of 40.6 and 41.9 dB, and an error vector magnitude (EVM) of 5.48%, 3.48%, respectively. In addition, it has a differential output voltage swing of 1.55 Vp-p with a dc power consumption of 635.3 mW.

MEMS gyroscope control system using a band-pass continuous-time sigma-delta modulator

This paper presents a MEMS gyroscope control system of using a high-order band-pass continuous-time sigma-delta modulator. Compared with a low-pass discrete-time sigma-delta modulator based solution, the band-pass modulator can considerably decrease the sampling frequency; moreover, the continuous-time architecture has an obvious advantage on PCB prototyping and shorter lead time of the implementation in hardware. System level simulations using MATLAB/Simulink show the proposed sixth order sigma-delta modulator can achieve a high SNR of 100 dB for an angular rate input with an amplitude of 200°/s and a frequency of 32 Hz. A PCB circuit implementation is simulated using Orcad/PSpice to analyze the stability, and implemented in hardware. Measurement of the power spectral density of the output bitstream reveals a noise floor of −90 dBV/Hz1/2. The prototype is tested on a rate table with an angular rate input, verifying that the principle of the approach of using an electro-mechanical band-pass sigma-delta modulator control system for a MEMS gyroscope.

Parameter optimization for a high-order band-pass continuous-time sigma-delta modulator MEMS gyroscope using a genetic algorithm approach

This paper describes a novel multiobjective parameter optimization method based on a genetic algorithm (GA) for the design of a sixth-order continuous-time, force feedback band-pass sigma-delta modulator (BP-ΣΔM) interface for the sense mode of a MEMS gyroscope. The design procedure starts by deriving a parameterized Simulink model of the BP-ΣΔM gyroscope interface. The system parameters are then optimized by the GA. Consequently, the optimized design is tested for robustness by a Monte Carlo analysis to find a solution that is both optimal and robust. System level simulations result in a signal-to-noise ratio (SNR) larger than 90 dB in a bandwidth of 64 Hz with a 200° s−1 angular rate input signal; the noise floor is about −100 dBV Hz−1/2. The simulations are compared to measured data from a hardware implementation. For zero input rotation with the gyroscope operating at atmospheric pressure, the spectrum of the output bitstream shows an obvious band-pass noise shaping and a deep notch at the gyroscope resonant frequency. The noise floor of measured power spectral density (PSD) of the output bitstream agrees well with simulation of the optimized system level model. The bias stability, rate sensitivity and nonlinearity of the gyroscope controlled by an optimized BP-ΣΔM closed-loop interface are 34.15° h−1, 22.3 mV °−1 s−1, 98 ppm, respectively. This compares to a simple open-loop interface for which the corresponding values are 89° h−1, 14.3 mV °−1 s−1, 7600 ppm, and a nonoptimized BP-ΣΔM closed-loop interface with corresponding values of 60° h−1, 17 mV °−1 s−1, 200 ppm.

A UHF current-mode continuous-time band-pass delta sigma modulator using fully balanced active inductor

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.

On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion

This paper describes issues and tradeoffs related to the design of undersampling delta-sigma modulators (DeltaSigmaMs) for wireless receivers. It proposes a new bandpass undersampling DeltaSigmaM architecture dedicated to multigigahertz frequencies. This paper is based on up-sampling in the feedback path to remove the analog mixer usually found in the modulator. Design equations are discussed for an optimum operating point when the input signal is at 1.8 GHz. The related design model can be applied to many communication standards. The underlying proposed architecture can receive high-frequency carriers modulated with signals of bandwidth as large as 5 MHz. In the proposed design, it converts the signal into digital data with a spurious-free dynamic range of 46 dB at a sampling frequency of 810.1 MHz. Design simulation, characterization, and implementation of the proposed modulator are done using a 0.13- mum CMOS technology.

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8---2 GHz bandwidth.

Manchester encoded bandpass sigma–delta modulation for RF class D amplifiers

An analysis of a continuous-time bandpass sigma–delta modulator in a configuration with an upconverter is given for a RF class D amplifier application. The upconverter multiplies the modulator pulse train with a synchronised clock signal and maps each modulator bit to an integer multiple k of a (+1, −1) or (−1, +1) pattern depending on the sign of the modulator bit. The upconversion is equivalent to an extension of Manchester encoding, which is usually defined for k=1. The analysis focuses on evaluating the impact of upconversion on the modulator coding efficiency and the average pulse period. A design equation is derived, which shows that coding efficiency is dependent only on the upconversion frequency ratio, while the average pulse period depends only on k. The equations provide a designer with a way of evaluating the trade-offs in the amplifier system and show that encoding with k=1 is the most efficient configuration for maximising coding efficiency and minimising switching power loss.

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.

Sixth-order programmable bandwidth bandpass sigma–delta modulator implemented with transmission lines

An implementation of a sixth-order bandpass continuous time sigma–delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter.

A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF

This paper presents a sixth-order continuous-time bandpass sigma-delta modulator (SDM) for analog-to-digital conversion of intermediate-frequency signals. An important aspect in the design of this SDM is the stability analysis using the describing function method. The key to the analysis is the extension of the linear gain model for the sampled quantizer with a phase uncertainty. The single-loop, one-bit SDM is tuned at 10.7 MHz, is sampled at 40 MHz, and achieves 67-dB signal-to-(noise+distortion) ratio in 200 kHz and 80 dB in 9 kHz. The third order intermodulation is at -82 dBc for a -13-dBFS input level. The 0.5-/spl mu/m CMOS chip occupies 0.9/spl times/0.4 mm/sup 2/ and consumes 60 mW at 3.3 V (digital) and 5.0 V (analog). The sample frequency is variable and can be set from 30 to 80 MHz.