Bandgap Reference Research Articles

A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems.

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

Design of Improved Band Gap Reference Circuit for CS-VCO Application Using 180nm CMOS Technology

Electronics engineers are currently faced with the task of designing linear and broad scale voltage regulated oscillator for analogue and a varied signal applications for a shorter design period of time. The Band gap reference source is used here to compensate the noise which affects the Phase lock loop operation from power supplied noise. A cascode current mirror based band gap reference current starved voltage controlled Oscillator (BG-CSVCO) is discussed in detailed as a new design strategy for reducing power supplied noise in Phase lock loop (PLL) applications. A cascode current mirror based band gap reference CS-VCO design is simulated and direct employing in 180nm Cadence CMOS technology. A frequency range of band gap reference CS-VCO is 0.009 GHz up to the 2.07 GHz for adjusting range of 0.5V to 1.8V with the power dissipation is 0.564mW. The VDD as supplied voltage was 1.8volt.

An LDO Circuit Design Based On On-chip Compensation

This paper proposes a liner low-dropout regulator (LDO) circuit using on-chip steady-state compensation technology. Firstly, a bandgap reference is designed with low temperature drift and low power consumption. Secondly, the on-chip compensation is adopted in the LDO, which can avoid the use of large off-chip capacitors and reduce the layout area of the LDO circuit. The circuit performances are verified in the TSMC 180 nm CMOS process. Test results show that temperature coefficient of the bandgap reference circuit is as low as 4.3 × 10-6 °C in the temperature range of -40°C to 125°C. The static current under the 3V power supply voltage is 4 μA. The LDO output voltage Vout is 1.8V . And the core area of the chip is 0.0848 mm2.

First-order Bandgap Reference Source Design with High Power Supply Rejection Ratio

In this paper, a first-order bandgap reference source with a high power supply rejection ratio (PSRR) is designed. To obtain a low-temperature coefficient, a first-order bandgap temperature coefficient compensation method is used by adjusting the resistor resistance of the positive and negative temperature coefficients, and the gate-source voltage of the current mirror transistor is kept constant to increase the PSRR value in the low-frequency band. A self-start circuit is added to make the circuit start up quickly out of the simple bias point. The simulation results show that the bandgap reference voltage source has a constant 1.25V reference voltage with a temperature coefficient of 8.55ppm/°C in the temperature range of -40 to 125°C. The circuit is simulated using Cadence software. The circuit can be applied to OLED constant current source circuits and power management circuits.

A high or low temperature compensation bandgap reference voltage with pre-regulated voltage circuit

分析了带隙基准电压分段补偿技术与基本原理, 提出一种具有预稳压功能的高低温补偿带隙基准电路。应用高低温补偿电路优化了温度系数, 设置预稳压电路提高了带隙基准电路的电源抑制比。基于0.35 μm标准CMOS工艺设计并绘制了电路及版图。仿真结果表明, 在-55~125℃范围内, 温漂系数仅为1.8×10-6/℃; 电源抑制比为-84.6 dB(在1 kHz下); 在2.6~5 V的电源幅度范围下, 电源抑制性能为19.6 μV/V。该电路可应用于高精度系统设计中。

A 2.2ppm/°C compensated bandgap voltage reference with a double-ended current trimming technique

A 2.2ppm/°C compensated bandgap voltage reference with a double-ended current trimming technique

High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and gm/ID Methodology

Bayesian optimization (BO) is popular for a analog circuit sizing problem recently. However, BO can only work well in small-scale circuit. Scaling BO to common circuit optimization (typically dimension > 10) is difficult due to the curse of dimensionality. In this article, we proposed a new BO algorithm (cBO), which can scale BO to more larger scale circuit and improve the optimization result. First, according to the fact that a specification of the analog integrated circuit is mainly determined by a few transistors, dropout strategy is adopted in our algorithm. At each iteration, only a subset of selected variables to be optimized. A variables selection strategy based on mutual information analysis and a new fill-in strategy are proposed. Second, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> methodology-based optimization strategy is proposed. Optimization variables are not width and the length of transistors, but <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{D}$ </tex-math></inline-formula> and length. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{D}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> have a direct relationship to circuit performance. This is equivalent to search in circuit feature space, which could achieve better performance and handle constraints more easily. Four commonly used circuits, including low dropout regulator, two stage amplifiers, Bandgap voltage reference (VR), and VR are used for validation. Compared with other high-dimensional BO, common BO, and commercial tools (Cadence ADE_GXL), the proposed algorithm is found to produce the best optimization result and best stability. And, the ablation study shows the effectiveness and efficiency of two ingredients of the proposed algorithm.

Correction: He et al. A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS. Electronics 2022, 11, 2869

In the published publication [...]

A Floating-Body Transistor-Based Power Amplifier for Sub-6-GHz 5G Applications in SOI CMOS 130-nm Process

A floating-body transistor based two stages power amplifier (PA) with lateral NPN based bandgap voltage reference (BVR) is implemented in a 130 nm Silicon-On-Insulator (SOI) CMOS process for sub-6GHz 5G applications. Floating-body (FB) transistors instead of traditional body-contacted (BC) transistors have been adopted in driver stage and power stage amplifiers of the proposed PA. On-chip input and output transformer baluns (TB) are customized designed for this PA which can realize impedance matching. Split push-pull structure is adopted in both driver stage and power stage with inter-stage matching networks. Incorporating bonding wire multi-physics models into input and output matching and power gain temperature compensation, the proposed PA can achieve maximum 25.6 dB power gain, 22.2 dBm output power and 28% power added efficiency (PAE) at 1 dB compression point (OP-1dB). The 3 dB bandwidth of the proposed PA is from 4.3 GHz to 6.4 GHz and the core size is 0.59 mm2. When the proposed PA is used for IEEE 802.11ac application and measured at VHT80 MCS9 (80MHz, 256-QAM), it can achieve 21.4 dBm output power and 24.8% PAE at 5.5 GHz operating frequency with −36 dB error vector magnitude (EVM).

A Sub-1-V 8.5-ppm/°C Sampled Bandgap Voltage Reference

This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled onto a capacitor. By sampling the voltages onto a capacitor, we eliminate the need for an opamp in the bandgap core, which tends to be the dominant source of noise and offset concerns in low voltage bandgap designs in scaled technologies. A prototype was designed and fabricated in 28nm TSMC HPC+ technology with a nominal output voltage of 108mV. It demonstrates a temperature coefficient of 8.5ppm/°C between −40°C and 125°C, and occupies an area of 0.0075mm2 while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.6\mu \text{W}$ </tex-math></inline-formula> of power.

A power-efficient acquisition front end for the Li-ion battery management systems

This paper presents a Coulomb sensing method-based power-efficient acquisition front-end (AFE) for Li-ion battery management systems (BMSs). The AFE, based on two self-calibrated incremental analog-to-digital converters (ADCs), measures the instant current flows in and out of the Li-ion battery, the cell voltage, and the internal and external temperature of the chip to compensate for the state of charge. A switched-capacitor CMOS bandgap reference (BGR) is proposed to obtain stable reference voltage over an operating temperature range of the BMS. A wake-up comparator indicates that a large charging and discharging current occurs while the BMS is in sleeping mode. This solution significantly reduces the obtained samples and has better power efficiency than an always-acquisition method. A prototype was fabricated in the 110-nm CMOS process, achieving a DNL of −0.85/+1.7 LSB and an INL of −3.2/+4.2 LSB. The total current consumption of the normal operation and the sleeping mode from a battery is 23 μA and 1.26 μA, respectively.

A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS

In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.

Design of a Power Regulated Circuit with Multiple LDOs for SoC Applications

In this paper, a power regulated circuit (PRC) is proposed for system-on-a-chip (SoC) applications. The proposed PRC is composed of a limiter, a bandgap reference (BGR), three low-dropout regulators (LDOs), and a bias generator. A high output voltage of an active rectifier is given to the limiter, which limits it to a desired supply voltage for circuits in PRC. The curvature-compensated BGR robust to process, voltage and temperature (PVT) variations are designed to provide a stable reference voltage for three LDOs. The three LDOs are implemented to generate regulated output dc voltages. The proposed PRC is designed and fabricated in 130 nm bipolar-CMOS-DMOS (BCD) technology with die area of 1.9 mm × 0.860 mm, including pads. The measurement results show that the limiter limits the input voltage of (6 V to 20 V) to 5.3 V. The BGR produces a stable reference voltage of 1.24 V with a power supply rejection ratio (PSRR) of −58.6 dB and −51.9 dB at 10 Hz and 1 kHz, respectively. The LDO_5V, LDO_3V, and LDO_1.5V generate regulated output dc voltages of 5 V, 3 V, and 1.5 V, respectively, with dc load regulations of 0.43 mV/mA, 0.70 mV/mA, and 0.28 mV/mA while delivering load currents of 300 mA, 100 mA, and 100 mA, respectively.

A Reference Source Circuit Design for Voltage Controlled Oscillator Chips

The basic principle and typical structure of the bandgap voltage reference source are introduced in detail in this paper. The performance index of the bandgap voltage reference is analyzed. The core circuit of a bandgap voltage reference source with good temperature characteristics and a high power supply rejection ratio (PSRR) is designed, in which a two-stage differential operational amplifier with a buffer stage is used, a start-up circuit without a capacitor is used to reduce the start-up time, and a common beta multiplication self-bias circuit is used to attenuate the effects of the power supply voltage. It is shown from the final HSPICE simulation results that the reference voltage temperature coefficient is approximately 7 ppm/°C within the range of -20 to 80°C in temperature, and the average PSRR can reach more than −56 dB within the range of 1 Hz to 10 kHz in frequency.

A high PSR LDO with adaptive loop switching control and feedforward ripple cancellation techniques

This paper proposed a low-dropout regulator (LDO) with adaptive loop switching control (ALSC) and high-pass filter-based feedforward ripple cancellation (HPFRC) techniques. The ALSC circuit can be utilized for wide-input-range LDO and provide a clean power supply for the bandgap reference (BGR) without a pre-regulator circuit. The power supply rejection (PSR) at low frequencies of the proposed LDO is insensitive to the limited PSR of BGR. In addition, the HPFRC circuit can enhance the mid-range PSR of the LDO. This circuit has been designed and verified in 0.25-μm BCD technology. The simulation results demonstrate that the output voltage of 5 V is stable with a 2.2 μF output capacitor when an input voltage from 5.25 V to 24 V is applied. The LDO consumes only 36.4 μA at full load, and the line and load regulation are simulated as 0.02 mV/V and 9.2 μV/mA, respectively. It achieves a PSR of –72 dB at 1 MHz for heavy loads.

Design and simulation of low dropout voltage regulator using 180nm technology

Low Dropout (LDO) Voltage Regulators are the linear regulators which drives upon a very small differential voltage. The main components of the Low dropout voltage regulators are Error amplifier, Pass device, voltage reference source and Voltage divider network. The low dropout voltage regulator uses a variable input to give a steady, constantly controlled, low-noise DC output voltage. This is a linear voltage regulator that includes a small voltage drop among the input as well as the output that works even when the output voltage is extremely close to the input voltage. The Error amplifier circuit which is one of the components in Low dropout voltage regulator is designed in the standard 180nm CMOS technology, with supply voltage of 1.6V, the gain of the error amplifier is 74db, Band-gap reference circuit is implemented to produce stable reference voltage which is independent of temperature variations. The bandgap reference voltage circuit gives the output voltage of 1.2V. The low dropout voltage regulator produces constant output voltage of 1.8V for the input voltage range 2.1V to 3.5V and it provides constant output voltage for load variations.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout

A full-MOSFET low temperature-coefficient (TC) and low power-supply-rejection-ratio (PSRR) bandgap reference (BGR) circuit with 6-bit high-precision programmable multilevel voltage output is presented, which is applicable for low-frequency human electroencephalogram (EEG) signal sensing system. The BGR is implemented based on 65 nm/1.8 V standard CMOS technology, accurate 64-level reference voltages by 5 mV resolution are realized with a novel tunable resistor-switch-array architecture, which are implemented by a compact multi-finger transistor-array (TA) placement manner for process variation-tolerant and layout area-efficiency. The pre-/post simulation results show that, with effectively achieving a low-variation 1.0033 V reference output voltage, TC value can be lower to 10 ppm/°C in a wide temperature range (TR) from -45 °C to 120 °C, the output reference voltage also shows significant feature by -56.2 dB in PSRR at 10 Hz application frequency. Furthermore, the 64-level output voltage by 5 mV-step from 0.765 V to 1.075 V is effectively and accurately operated by external 6-bit programmable logical controls, and this functionality can be flexibly employed to multilevel biasing supply to core functional modules within electroencephalogram (EEG) sensor chip.

A high accuracy and configurable voltage (1.2/1.8/2.5/3.3 V) bandgap reference with base current compensation for DC–DC converters

A high accuracy and configurable voltage (1.2/1.8/2.5/3.3 V) bandgap reference with base current compensation for DC–DC converters

A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from a 1-V supply. The 2.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> XO features a low-frequency inaccuracy of 4 ppm/V. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.