Band Low Noise Amplifier Research Articles

A study on develop the High-Performance Wide - Band LNA for use with IEEE frequency

In this research, a low-noise amplifier (LNA) with uniform growth, silent operation, and absolutely brilliant uniformity is suggested to be utilized in bandwidth transmitters, with a comparative channel capacity (RBW) of 110%. To enhance extended the reach, researchers present a cascode with dual feedbacks and a wide bandpass (BPDWB) matching network formed from bias and parasitic characteristics. The techniques for constructing a corresponding networking are also shown, and measurements indicate that the channel's resonance frequency is a great pairing for the required resistance in the range from through 3.5 GHz. Resistance matched precision and efficiency in prediction are both boosted by the envisaged BPDWB networks. Paper presents a low amplifiers (LNA) in 0.25 m GaAs father made high mobility electrons semiconductor (GaAs pHEMT) developers and researchers NF0.55 at mhz. Additionally, for the range of frequency of 8.5-20 MHz, overall bit error rate (NF) is somewhere between 2.19 to 3.23 dB, while another NF maximum (vase: internet: mia2bf00852: mia2bf00852-math-0012) varied between 1.55 - 2.91 db. At top of just that, a two-tone test with a frequency separation of 50 MHz demonstrates that the suggested LNA may accomplish high IIP3 of 0.96 frequency range.

Low-Noise Amplifier with Bypass for 5G New Radio Frequency n77 Band and n79 Band in Radio Frequency Silicon on Insulator Complementary Metal-Oxide Semiconductor Technology.

This paper presents the design of a low-noise amplifier (LNA) with a bypass mode for the n77/79 bands in 5G New Radio (NR). The proposed LNA integrates internal matching networks for both input and output, combining two LNAs for the n77 and n79 bands into a single chip. Additionally, a bypass mode is integrated to accommodate the flexible operation of the receiving system in response to varying input signal levels. For each frequency band, we designed a low-noise amplifier for the n77 band to expand the bandwidth to 900 MHz (3.3 GHz to 4.2 GHz) using resistive-capacitance (RC) feedback and series inductive-peaking techniques. For the n79 band, only the RC feedback technique was employed to optimize the performance of the LNA for its 600 MHz bandwidth (4.4 GHz to 5.0 GHz). Because wideband techniques can lead to a trade-off between gain and noise, causing potential degradation in noise performance, appropriate bandwidth design becomes crucial. The designed n77 band low-noise amplifier achieved a simulated gain of 22.6 dB and a noise figure of 1.7 dB. Similarly, the n79 band exhibited a gain of 21.1 dB and a noise figure of 1.5 dB with a current consumption of 10 mA at a 1.2 supply voltage. The bypass mode was designed with S21 of -3.7 dB and -5.0 dB for n77 and n79, respectively.

Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation

We report the impact from channel composition on the cryogenic low-noise performance at low dc power for a 100-nm gate-length InGaAs-InAlAs-InP high-electron mobility transistor (HEMT). Two indium (In) channel compositions, 65% and 80%, were studied by dc and RF characterization at 300 and 5 K. For the cryogenic low-noise optimization, it was important to increase the transconductance to gate–source capacitance ratio in the weak inversion region implying that a higher maximum cutoff frequency in the HEMT does not guarantee lower noise. The HEMT noise performance was obtained from noise measurements in a hybrid three-stage 4–8-GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band) low-noise amplifier (LNA) down to 300- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W dc power dissipation. While the HEMT LNA noise performance for both the channel compositions at 300 K was found to be comparable, the HEMT LNA at 5 K with 65% In channel showed a minimum noise temperature of 1.4 K, whereas the noise temperature in the HEMT LNA with 80% In channel HEMTs increased to 2.4 K. The difference in the noise became more pronounced at reduced dc power dissipation. The ultralow dc power of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W demonstrated for a cryogenic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band LNA with an average noise temperature of 2.9 K and 24-dB gain is of interest for future qubit read-out electronics at 4 K.

Frequency-Reconfigurable Dual-Band Low-Noise Amplifier With Interstage Gm-Boosting for Millimeter-Wave 5G Communication

A differential low-noise amplifier (LNA) for the 5G n257 band and a frequency reconfigurable differential LNA for both the 5G n257 and n260 bands (26.5–29.5 and 37–40 GHz), fabricated in a 65-nm CMOS process, are presented. Both LNAs achieve better gain and noise figure performances due to the use of magnetically coupled gm-boosting in the common-gate stage of a cascode amplifier. Furthermore, the frequency-reconfigurable LNA uses frequency reconfigurable matching circuits at the input, interstage, and output to achieve optimal noise and gain matchings for each band. The single band LNA has a core chip area of 0.11 mm2, a peak gain of 11.9 dB, a 3-dB bandwidth of 5.3 GHz, and a noise figure of 2.79 dB at 28.5 GHz. The dual-band LNA is capable of dual-band operation due to the reconfiguring matching circuits with switched coupled inductors (SCIs) and switched capacitors. It has a core chip area of 0.12 mm2, peak gains of 11.1/8.5 dB, 3-dB bandwidths of 4.8/9.4 GHz, and minimum noise figures of 3.49/4.01 dB at 28.5/38 GHz, respectively.

A 120–140-GHz LNA in 250-nm InP HBT

This letter presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band low-noise amplifier (LNA) in 250-nm InP HBT technology for the next-generation wireless applications. The LNA has a measured peak gain of 13 dB, a 3-dB bandwidth greater than 20 GHz (120–140 GHz), and a measured noise figure (NF) of less than 6 dB in the band. A reduction in the 3-dB bandwidth from simulation was observed during the measurements which was attributed to the substrate waves using full chip electromagnetic (EM) simulation. EM simulations show that a partial or complete removal of the back side metallization of the InP substrate, holes in metal-1 ground plane, or a strategic placement of through-substrate vias suppress these substrate waves. To the authors’ knowledge, this is the first 120–140-GHz LNA in the InP 250-nm HBT technology.

Design of Common Gate Current-Reuse Noise Cancellation UWB Low Noise Amplifier in 90nm CMOS

In this paper, an ultra-wide band (UWB) low noise amplifier (LNA) is implemented by using 90nm RF CMOS technology. The designed LNA achieves high flat band gain (S21) and low noise figure (NF) in the frequency of interest. The proposed LNA operates in the frequency range of 3GHz to 8GHz. In this work, wide band matching is achieved by designing common gate configuration at the input stage. The current reuse and noise cancellation techniques are introduced to improve flat band gain and minimize both noise figure and power consumption. The noise figure is improved by cancelling dominant noise sources with additional hardware. The proposed LNA attains flat band gain of 26.5dB and input matching less than -12dB for entire UWB band. This work achieves noise figure of 2.1dB to 2.59dB in frequency band of interest. Additionally, power consumption of the circuit is 20mW at 1.8V supply voltage.

DC Power-Optimized Ka-Band GaN-on-Si Low-Noise Amplifier With 1.5 dB Noise Figure

A <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band low-noise amplifier for low-consumption robust receivers is presented in this letter. The monolithic microwave integrated circuit (MMIC) is designed on a 100 nm GaN-on-Si technology provided by OMMIC foundry and decibel gain, average noise figure (NF) of 1.5 dB, with input–output return losses better than 15 dB in the whole 27–31 GHz design band. Large signal measurements show a OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dBcp</sub> of +16 dBm and survivability to RF input power verified up to +25 dBm without showing critical degradation. These performances have been achieved with only 150 mW dc power consumption in linear operating condition, 30% less than other <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band GaN LNAs published in the open literature.

Low Noise and high linearity Wide band Low Noise Amplifier for 5G Receiver Front End System

This work Demonstrates a wideband LNA for 5G receiver front end modules with high linearity, Low noise reused topology has an inter stage wideband inductor based two common source cascade stages. The configuration provides the bias current; better Noise figure increases the forward gain. By providing RC Series network at gate terminal of second stage the return losses are reduced and stability will be increased. After pre and post simulation all parameters are better than the existing LNAS. After post simulation results, the Noise figure is achieved less than 1dB and forward gain as flat 16dB for wide band width of 1.5 – 5.5 GHz. At the 1dB compression point the output is 20dbm achieved and OIP3 IS +40dbm is achieved. The chip size of an LNA along with pad is 0.64mm2. The design is GaAsp HEMT process at 50nm technology.

A V-Band Low-Power Compact LNA in 130-nm SiGe BiCMOS Technology

This letter presents the design of a ${V}$ -band low-power compact low-noise amplifier (LNA) in a 130-nm SiGe BiCMOS technology. For the low-power and low-noise requirements, transistors need to operate with low-voltage supply and low current density, which comes at the cost of lower gain per BJT stage. We use a technique to cancel the Miller capacitance in a single-stage differential amplifier and achieve high-gain, low-power, and low-noise simultaneously. The circuit topology is analyzed, and the transistor core layout and the matching network design considerations are discussed. The measured circuit shows a peak gain of 14.1 dB in a 3-dB bandwidth from 44 to 67 GHz while consuming 5.1 mW. Experimental results show an output power of 7.1 dBm at 1-dB compression with an associated power-added efficiency of 30%. The simulated noise figure is 3.3 dB at the center frequency. To the best of the authors’ knowledge, the highest figure of merit among ${V}$ -band LNAs based on silicon is reported.

Millimeter-wave Frequency Reconfigurable Low Noise Amplifiers for 5G

In this brief, designs of two millimeter wave (mmWave) reconfigurable multi band low noise amplifiers (LNA) are presented targeted for fifth generation (5G) communications. A reconfigurable tunable load based on electrical and magnetic tuning is proposed to cover three mmWave frequency bands for 5G, i.e., 24 GHz, 28 GHz and 39 GHz. Two LNA structures are designed and fabricated using 45nm CMOS SOI technology. The first toplogy (LNA1) is composed of a single input wideband matching circuit to cover frequency operations from 24 GHz to 40 GHz. On the other hand, second topology (LNA2) uses three separate narrowband match inputs, one for each frequency band, with combined output. Design methodology of passive and active devices is presented towards compact integration of LNAs for systems such as, phased arrays. Ground plane and its impact on the performance parameters is also discussed in this brief. Measurement results show a wideband noise figure (NF) ranging from 3.8 dB to 4.9 dB and gain of 8.5 dB to 12.5 dB for LNA1 at different bands. Similarly, LNA2 exhibits NF of 4.5 dB to 5.5 dB and gain of 9.5 dB to 15.5 dB across all bands. Total area (including pads) of LNA1 and LNA2 are 0.316 mm2 and 0.695 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

A Submilliwatt K-Band Low-Noise Amplifier for Next Generation Radio Astronomical Receivers in 65-nm CMOS Process

An ultralow-power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band low-noise amplifier (LNA) for next generation radio astronomical receivers fabricated in 65-nm CMOS technology is presented in this letter. A gate–source transformer feedback is utilized for the simultaneous noise and impedance matching. In order to achieve high gain with limited dc power consumption ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {dc}}$ </tex-math></inline-formula> ), a single-ended neutralization technique is applied to the circuit. According to measurement, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band LNA achieves a 19.1-dB small signal gain with 2.8-GHz 3-dB bandwidth (21.2–24 GHz) and noise figure of 3.6 dB with only 0.99 mW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {dc}}$ </tex-math></inline-formula> . To the best of author’s knowledge, this LNA shows the highest figure of merit (FoM), which is 7071 1/W, among published <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band low-power LNAs.

V-Band GaAs Metamorphic Low-Noise Amplifier Design Technique for Sharp Gain Roll-Off at Lower Frequencies

In this letter, we present the design of a V- band low-noise amplifier for intersatellite crosslink receivers. The test vehicle, realized on industrial metamorphic gallium arsenide technology, operates from 57 to 66 GHz exhibiting 23-dB gain and an average 1.8-dB noise figure. Particular attention was devoted to the analysis and synthesis of an alternative bias injection topology to obtain a sharp gain roll-off at lower frequencies, thus avoiding the insertion, at system level, of an image-reject filter.

Design of reconfigurable multi-band low-noise amplifiers for 802.11ah/b/g and DCS-1800 applications

In this paper two reconfigurable multi band low-noise amplifiers, namely LNA1 for 802.11ah/b/g and LNA2 for 802.11ah/b/g, DCS-1800 applications using tank circuits are presented. Dual feedback is used to achieve multi band operation in both the LNAs. Power dissipation of the LNAs is reduced by employing current-reuse and forward body-biasing in the first stage of the LNAs. The novelty of the proposed approach lies in the fact that the reconfigurability of the LNAs for multi bands is achieved using simple tank circuits without requiring any additional biasing arrangement. The LNAs are designed using UMC 180 nm RFCMOS process. The post layout simulation results of LNA1 showed a power gain of 9.3 dB with noise figure of 3.7 dB, IIP3 of −2.19 dBm, DC power dissipation of 16.5 mW at 900 MHz and a power gain of 10.6 dB, noise figure of 3.1 dB, IIP3 of −2.7 dBm at 2.4 GHz. In LNA2 one common-source stage is added for further gain improvement and one more tank circuit is added to operate it additionally in GSM band, namely DCS-1800. Post layout simulation of LNA2 showed a power gain of 16.1 dB with noise figure of 4.6 dB, IIP3 of −6.57 dBm, DC power dissipation of 24.9 mW at 900 MHz; a power gain of 14.7 dB with noise figure of 5.4 dB, IIP3 of −4.34 dBm at 1.8 GHz and a power gain of 16.2 dB, noise figure of 3.6 dB, IIP3 of 0.57 dBm at 2.4 GHz.

Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.

A 180-nm X-Band Cryogenic CMOS LNA

This letter presents the measurement results of a 180-nm complementary metal–oxide–semiconductor (CMOS) $X$ -band low-noise amplifier (LNA) at both 77 and 300 K. The designed LNA provides $S_{11}$ and $S_{22}$ below −10 dB at both temperatures within 6.4–7.4 GHz band. At 300 K, the voltage gain of the designed LNA is higher than 12.5 dB, and it provides an average noise temperature of 275 K, as well as −1 dBm IIP3. At 77 K, the LNA has approximately an 18-dB voltage gain, 78-K noise figure (NF), and −3 dBm IIP3. The presented work is the first implemented $X$ -band cryogenic CMOS LNA in the literature.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

Highly linear wide band low noise amplifiers: A literature review (2010–2018)

Wideband (WB) CMOS low noise amplifier (LNA) design requires linearity consideration for better performance across the entire band because the increase in the number of interferers put severe constraints on system linearity requirements. In this paper, a literature review is presented within academic papers published with good linearity results on WB LNA between 2010 and 2018. Results of sample LNA designs are discussed with emphasis on bandwidth, noise figure (NF), gain and matching tradeoffs. This review provides useful insights on linearization techniques, the trade-offs consideration between the main parameters and also aids the creation of new ideas in this field. In addition, the designed LNAs have been compared with considering a new overall factor.

Performance analysis of low power LNA using particle swarm optimization for wide band application

This paper characterizes a design analysis of low power (LP) and low voltage (LV) optimized low noise amplifier (LNA) for wide band applications. With review discussion on design challenges of LP and LV, a new biasing metric has been introduced for radio frequency analog circuit. The proposed LNA consists of two stages, the first stage is a current reuse topology, in which a combination of PMOS transistor stack on top of NMOS transistor has been used with series inductive peaking in the feed-back loop. It helps a lot to achieve the target of LP and LV, while the second stage is a mutually coupled CS stage, used for wideband matching to enhance the bandwidth and noise figure (NF). For optimization of passive component parameters of proposed LNA, particle swarm optimization (PSO) algorithm has been used. All the simulations have been done for a range of frequency 0–35 GHz in Cadence Virtuoso software 45-nm CMOS technology. The results quoted 18.57 dB maximum voltage gain, 2.4 dB NF, 17.1 dB S11, 16.6 dB S21, at frequency 25.4 GHz with 0.8 V, 1.6 mW broad band LNA.

Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

A Survey on Ultra Wide Band and Narrow Band Low Noise Amplifiers for Wireless Transceivers

A Survey on Ultra Wide Band and Narrow Band Low Noise Amplifiers for Wireless Transceivers