Band-edge Effective Work Function Research Articles

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

In this paper, the band-edge work function performance is systematically investigated and modulated via novel nitrogen plasma treatment (NPT) with the advanced PMOS1st (TiN/TiN/TiAlC) and NMOS1st (TiN/TiN) laminated stacks for the fabricated PMOS capacitors. The basic multi-VT performance is strongly modulated by controlling NPT process. 1) Flatband voltage (VFB) shifts towards band edge are obtained as +120 mV (undiluted), +430 mV (diluted) for PMOS1st and +80 mV (undiluted), +210 mV (diluted) for NMOS1st. 2) By manipulating the NPT process from undiluted and diluted case, it can provide significant high band-edge effective work function ranging from 4.89 eV (undiluted) to 5.21 eV (diluted) for PMOS1st and 5.22 eV (undiluted) to 5.35 eV (diluted) for NMOS1st laminated stack, respectively. 3) NPT diluted with hydrogen is observed to maintain ultralow bulk trap density (1.11 × 1011 cm−2 for PMOS1st and nearly zero for NMOS1st) and interface trap density (3.34 × 1011 eV−1 cm−2 for PMOS1st and 6.45 × 1011 eV−1 cm−2 for NMOS1st). The significant band-edge work function modulation and very low bulk and interface trap density demonstrate the novel NPT with PMOS1st/NMOS1st laminated stack is very promising to achieve the target of PMOS low-power application in the further technology node.

Band-Edge Work Function Obtained by Plasma Doping TiN Metal Gate for nMOS Device Application

This paper proposed, for the first time, that the band-edge effective work functions (EWFs) are achieved by employing PH3 plasma doping (PLAD) TiN metal gate for nMOS device application under replacement metal gate and high dielectric constant (k) dielectric/metal gate last nMOS device. The effects of PLAD energy, dose, gas mixture, and postdoping cleaning procedure on the EWF, EOT, and properties of TiN/HfO2/ILSiO2 gate-stack are investigated; the corresponding possible mechanisms are discussed. Suitable low threshold voltages of nMOSFETs are obtained, while shrinking the EOT. It reduces the corner effect on trench gate doping uniformity, which is induced by shadowing effect in the beam-line implantation technology, to a minimum. It has the potential for the further aggressively scaled 3-D CMOS device and beyond application.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ion-implanted TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ILSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ILSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Attainment of dual-band edge work function by using a single metal gate and single high-k dielectric via ion implantation for HP CMOS device

Attainment of dual band-edge effective work functions by using a single metal gate and single high k gate dielectric via P/BF2 implantation into a TiN metal gate for HP HKMG CMOS device applications are investigated under a gate-last process flow for the first time. The flat band voltage (VFB) modulations of about −750mV/570mV for N-/P-type MOS device with P/BF2 implanted TiN/HfO2/ILSiO2 gate stack are obtained respectively in the experiment range. Suitable low threshold voltages of CMOSFETs are gotten while simultaneously shrinking the EOT. The effects of P/BF2 ion implantation energy, dose and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate stack are studied, the possible mechanisms are discussed. This technique has been successfully integrated into the fabrications of aggressively scaled HP HKMG CMOSFETs and 32 CMOS frequency dividers under a gate-last process flow.

Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (Vt) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2 interface during forming gas anneal together with low O concentration in the TiN enables low NMOS Vt. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS Vt.

Demonstrating Valence Band-Edge Effective Work Function by Aluminum Implantation in High-k/Metal Gate p-MOSFET with Incorporated Fluorine

This work demonstrates the valence band-edge effective work function (φm,eff) of a titanium nitride (TiN) gate with a hafnium oxide (HfO2) dielectric using a cost-effective, low-complexity gate-first integration scheme. Aluminum (Al) ion implantation following TiN gate stack formation yielded a φm,eff of 5.0 eV without an equivalent oxide thickness penalty. Additionally, the incorporation of fluorine (F) into the HfO2 dielectric by the channel implantation approach further improved φm,eff to 5.1 eV. This technique for modulating φm,eff has potential for threshold-voltage tuning without any process complexity in high-k/metal gate low-power applications.

(Invited) Band-Edge Effective Work Functions by Controlling HfO2/TiN Interfacial Composition for Gate-Last CMOS

Effective work function (EWF) changes of TiN/HfO2 annealed at low temperatures in different ambient environments are correlated to the atomic concentration of oxygen, nitrogen, and aluminum at the metal/dielectric interface. Low EWFs (4.0 eV) are obtained by allowing aluminum to migrate to the TiN/HfO2 interface during a forming gas anneal. High EWFs (5.1 eV) are achieved with anneals that incorporate oxygen throughout the TiN with [O] = 2.8x1021 cm-3 near the TiN/HfO2 interface. First-principles calculations indicate the exchange of O and N atoms near the TiN/HfO2 interface cause the formation of dipoles that increase the EWF.

Fluorine implantation for effective work function control in p-type metal-oxide-semiconductor high-k metal gate stacks

The instability of the p-type metal effective work function of high-k/metal gate metal-oxide-semiconductor stacks after high temperature treatment results in device threshold voltage shifts and is one of the big challenges for the gate-first integration of high-k dielectrics in the future complementary metal-oxide semiconductor process flow. The exact cause of this instability is a subject of intense debate. In this article, it is shown that by implanting the gate stack with a fluorine dose of 1015 cm−2, it is possible to achieve an appropriate silicon valence band-edge effective work function of 5.1 eV for p-type metal-oxide-semiconductor devices. It is also shown that the fluorine doping can be accomplished not only with F+, but also with BF2+ ions. The influence of the implantation energy on the obtained effective work function is demonstrated and discussed. The origin of the induced shift is also discussed. Leakage current measurements show that the leakage properties of high-k stacks are not worsened by F implantation, while the implantation of BF2 slightly affects the leakage currents.

Characteristics of a band edge p-channel metal-oxide-semiconductor field effect transistors fabricated with a high-k /WAlx/TiSiN gate stack

A metal/high-k gate stack with a p-type band edge effective work function (EWF) of about 5.0 eV is demonstrated using a thin WAlx capping layer. The WAlx stack exhibits a lower threshold voltage (higher flatband voltage) value and better equivalent oxide thickness scalability than previously reported high EWF gate stacks using an AlOx cap. The WAlx cap p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) show significantly improved negative bias temperature instability (NBTI) characteristics than AlOx-capped pMOSFETs, which is attributed to negligible diffusion of Al into the interfacial oxide layer adjacent to the Si substrate.

Band-Edge High-Performance Metal-Gate/High-$\kappa$ nMOSFET Using $\hbox{Hf}{-}\hbox{Si}/\hbox{HfO}_{2}$ Stack

A record high electron mobility (248 cm2/V middots at E eff of 1 MV/cm) was obtained at T inv of 1.47 nm, with a band-edge effective work function, by a Hf-Si/HfO2 stack using gate-last process, resulting in I ON of 1178 muA/mum (I OFF of 100 nA/ mum ) at V dd of 1.0 V for a 45-nm gate nMOSFET without strain-enhanced technology.

Extreme Scaled Gate Dielectrics By Using ALD HfO2/SrTiO3 Composite Structures

A sub 1-nm equivalent oxide thickness (EOT) gate stack with conduction band edge effective work function is demonstrated with an ALD deposited HfO2/SrTiO3 based composite material. An EOT reduction of 0.2 nm as compared to the HfO2 reference is obtained after applying a high thermal budget in a gate first transistor flow. A comparison with ALD HfO2/La2O3 and HfO2/MgO composite stacks is made. Results suggest that the EOT reduction and threshold voltage shift (Vt) are determined by the Sr, La or Mg diffusion inside the dielectric stack and into the interface oxide after a thermal treatment. The onset of this diffusion is temperature dependent and differs from stack to stack.

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Conduction band-edge effective work functions (<formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex> </formula>) are demonstrated with <formula formulatype="inline"><tex>$\hbox{TaC}_{x}$</tex></formula> and TiN by means of <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capping of <formula formulatype="inline"><tex>$\hbox{HfSiO}_{x}$</tex></formula> in a gate-first process flow with CMOS-compatible thermal budget. With <formula formulatype="inline"><tex>$\hbox{TaC}_{x}$</tex></formula>, a 10- <formula formulatype="inline"><tex>$\hbox{\bf \AA}$</tex></formula>-thick <formula formulatype="inline"><tex>$ \hbox{La}_{2}\hbox{O}_{3}$</tex></formula> cap results in a <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$ </tex></formula> of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1–2 <formula formulatype="inline"><tex>$\hbox{\bf \AA}$</tex></formula>) and unaffected electron mobility. With TiN, non-nitrided <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capping results in a smaller <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex></formula> reduction at a larger EOT increase, while with post-cap nitridation, the TiN <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex></formula> is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capped stacks. </para>

Dual layer SrTiO 3/HfO 2 gate dielectric for aggressively scaled band-edge nMOS devices

We have fabricated TiN/Poly-Si gated MOS devices with SrTiO 3/HfO 2 dual layer gate dielectric. These gate dielectrics show EOT (Equivalent Oxide Thickness) scaling of less than 0.7 nm as well as large V fb shift in the nMOS direction after conventional gate first process. A sweet spot is observed for 0.5 nm SrTiO 3 where a band-edge effective work-function is obtained with improved EOT, reduced gate leakage and minimal hysteresis increase. But Sr diffuse into the interfacial layer leads to interface degradation. It is shown that proper PDA (post-deposition anneal) can improve interface quality while maintaining thinner EOT.

Metal gate work function engineering using AlNx interfacial layers

Metal gate work function enhancement using thin AlNx interfacial layers has been evaluated. It was found that band edge effective work functions (∼5.10eV) can be achieved on hafnium-based high dielectric constant (high-k) materials using the AlNx interfacial layer and TiSiN electrodes. It was also found that the effective work function enhancement by the AlNx interfacial layer increased when the concentration of SiO2 in the gate dielectric was increased. Thus, the enhancement was minimal for HfO2 and maximum for SiO2. A model is proposed to explain these results and a bonding analysis is presented to support the proposed model.