Backside Of Si Wafer Research Articles

A Novel Dicing tape for WLCSP Using Stealth Dicing Through Dicing tape and Back Side Protection-Film

Abstract Market demand of information terminals for Internet of Things (IoT) is increasing. So market situation requires various semiconductor packages. Wafer Level Chip Size Package (WLCSP) is one of the most important technology among them. We selected stealth dicing (SD) as a manufacturing method for WLCSP because the cutting speed is higher than blade dicing and the yield of semiconductor chip is higher than blade dicing. But, SD process still has some technical issues. In some cases, when the laser is irradiated from circuit side (from surface side of Si wafer), the metal pattern in circuit might prevent the laser focusing. In this case, the laser should be irradiated from backside of Si wafer through dicing tape. We have already developed a transparency suitable dicing tape for the SD process, but the base film material of the dicing tape is poly vinyl chloride (PVC) which is not becoming to conform with some of recent environmental standard. Market situation requires poly olefin (PO) dicing tape because of global environmental consideration. We developed PO dicing tape for SD process through dicing tape by conducting various evaluations. In this study, we report details of the development process of novel PO base film dicing tape with the same performance as PVC base film dicing tape and successfully separated a 12 inch silicon mirror wafer into 1 mm die squares and 12 inch silicon mirror wafer with the back side protection-film into 6 mm die squares.

High-detectivity and -stability multilayer-graphene/Si-quantum-dot photodetectors with TiOx back-surface passivation layer

We first report Si quantum dots (SQDs)-embedded SiO2 (SQDs:SiO2) multilayers (MLs)/Si photodetectors (PDs) using multilayer graphene (MLG) transparent conductive electrode (TCE) and TiOx back-surface passivation layer. With increasing number of graphene layer (Ln) to 5, the sheet resistance of the MLG TCE sharply decreases to ∼273 Ω/sq whilst the work function gradually increases to ∼4.71 eV, indicating p-type doping, useful for collection of photo-excited carriers at the MLG/SQDs:SiO2 MLs interface. At Ln = 4, the PD without TiOx exhibits best performance of 0.340 AW-1 responsivity (R) and 3.21 × 109 cm Hz1/2 W−1 specific detectivity (D*) at the peak wavelength. With TiOx on the back side of Si wafer (Ln = 4), the R slightly increases to 0.351 AW-1, but the D* is greatly enhanced to 9.42 × 1011 cm Hz1/2 W−1, resulting from the sharp reduction of the dark current by the suppression of the carrier recombination at the Si/TiOx interface. The PD performance is almost consistent for 1000 h in air, irrespective of the use of the TiOx layer. These behaviors are much better than ever achieved in graphene/Si wafer PDs.

Improvement of GaP crystal quality and silicon bulk lifetime in GaP/Si heteroepitaxy

The GaP crystal quality and Si bulk lifetime of GaP/Si heterostructures, grown by molecular beam epitaxy, are investigated. The Si bulk lifetime is reduced by over one order of magnitude after thermal deoxidation at high temperatures (>700°C). This significant reduction of the bulk lifetime is not observed when 150nm-thick SiNx film is present on the backside of Si wafer, which can act as a diffusion barrier and/or getter. In addition, a 15nm-thick GaP layer grown on the front side of Si wafer with SiNx on the backside shows a high crystal quality of GaP with a low crystalline defect density of 1.1×105cm−2. Moreover, the Si bulk lifetime is determined to be 1.83ms with a-Si:H passivation at an injected minority-carrier density of 1×1015cm−3, indicative of no bulk lifetime degradation. The high crystallinity of GaP and improved Si bulk lifetime are beneficial to improve photovoltaic device performance of III–V compound solar cells integrated with Si solar cells.

Alternative method to fabricate microdevices on a freestanding Si3N4 window

In this paper, the authors introduced a novel method for the fabrication of microdevices on freestanding Si3N4 thin-film windows with a single-side mask aligner. A thin-film microdevice located on the front surface of such a freestanding window was demonstrated, where the backside of Si wafer was performed with KOH wet etching. The results showed that an alignment error could be controlled in condition less than 20 μm. By using the freestanding device, a weak change in local temperature under an e-beam in a scanning electron microscope (FEI QUANTA 600F) was detected with better sensitivity.

Mitigation of Arsenic Contamination on the Back Side of Si Wafer Using SiO2 Protection Layer for III-V on Si Heterogeneous Epitaxy

In this paper, we have investigated a pathway to mitigate the arsenic (As) cross-contamination on a back side Si wafer during GaAs growth by metal-organic chemical vapor deposition (MOCVD). Without a proper protocol doing a III-V on Si heterogeneous epitaxy, we have observed high levels of the As concentration on the back side Si wafer, easily in excess of 1 × 1020 atoms/cm3 by secondary ion mass spectrometry (SIMS) analysis and 1015 atoms/cm2 by total reflection X-ray fluorescence (TXRF) analysis, after GaAs growth on Si. This known level of contamination on wafers would disqualify them for fabrication in existing Si VLSI fabs. In order to mitigate the As cross-contamination, we have proposed a SiO2 protection layer on the back side of the Si wafer. From both SIMS and TXRF analysis, the proposed scheme has dramatically lowered the back side as concentration to 1.5 × 1016 atoms/cm3 by SIMS and 1.0 × 1010 atoms/cm2 by TXRF.

Silicon Micro-Fabrication Technologies for Micro-Filters

Silicon micro-fabrication techniques allow for the development of microfluidic systems with very accurate control of size and uniformity of structures. In this paper we report on the silicon fabrication process of micro-filters for versatile application in fluidics systems. Micro-filters are composed of an ordered array of pillars and supply channels. Depending on pillar pitch, they can be used for, e.g., electrophoresis, chromatography and purification of biological mixtures. In this paper we focus on high performance liquid chromatography. The process that we have developed for micropillar fabrication consists of defining first 1μm diameter pillars with an inter-pillar distance of 1μm or less in an oxide hard mask with a DUV stepper, stitching is used to form few cm long patterns across the 200mm wafers. Second, the supply channels are defined with 1× alignment lithography. After definition of supply channels, deep reactive ion etching of silicon is performed with an optimised recipe to etch submicron pillars and supply channels of 100μm wide at the same time. The simultaneous etch of both structures avoids complex lithography steps otherwise necessary to protect the pillars while etching the supply channels or vice versa as would be done conventionally. Wafers are then anodically bonded to 200mm Pyrex wafers in order to seal the channels. Pyrex wafer also allows the use of optical detection system. Feed through holes for accessing the supply channels are etched on the backside of Si wafer. Filter characterization has been performed: a plate height of 1μm was measured and successful separation of 3 coumarin dyes is achieved.