Mitigation of Arsenic Contamination on the Back Side of Si Wafer Using SiO2 Protection Layer for III-V on Si Heterogeneous Epitaxy

Abstract

In this paper, we have investigated a pathway to mitigate the arsenic (As) cross-contamination on a back side Si wafer during GaAs growth by metal-organic chemical vapor deposition (MOCVD). Without a proper protocol doing a III-V on Si heterogeneous epitaxy, we have observed high levels of the As concentration on the back side Si wafer, easily in excess of 1 × 1020 atoms/cm3 by secondary ion mass spectrometry (SIMS) analysis and 1015 atoms/cm2 by total reflection X-ray fluorescence (TXRF) analysis, after GaAs growth on Si. This known level of contamination on wafers would disqualify them for fabrication in existing Si VLSI fabs. In order to mitigate the As cross-contamination, we have proposed a SiO2 protection layer on the back side of the Si wafer. From both SIMS and TXRF analysis, the proposed scheme has dramatically lowered the back side as concentration to 1.5 × 1016 atoms/cm3 by SIMS and 1.0 × 1010 atoms/cm2 by TXRF.