Backside Inductively Coupled-plasma Etching Research Articles

Two-step thinning fabrication of giant magnetoresistance sensors for flexible applications

Spin valve giant magnetoresistance (GMR) sensors were prepared by a two-step thinning method combining grind thinning and inductively coupled plasma (ICP) etching together. The fabrication processes of front GMR sensors and backside ICP etching were described in detail. Magnetoresistance ratio of about 4.24% and coercive field of approximately 11 Oe were obtained in a tested bendable GMR sensor. The variations of the magnetic property in GMR sensors were explained mainly from the temperature, ion beam damage and mechanical damage generated by the fabrication process.

A micromachined SiGe HBT ultra‐wideband low‐noise amplifier by BiCMOS compatible ICP deep‐trench technology

AbstractIn this article, we demonstrate that the power gain (S21) and noise figure (NF) performances of a SiGe HBT Ultra‐Wideband Low‐Noise Amplifier (UWB LNA) can be remarkably improved by removing the silicon underneath the UWB LNA with BiCMOS‐process compatible backside inductively‐coupled‐plasma (ICP) deep trench technology. The results show that increases of 1.9 dB (from 11.2 dB to 13.1 dB) and 4.2 dB (from 7.7 dB to 11.9 dB) in S21, and decreases of 0.59 dB (from 5.08 dB to 4.49 dB) and 0.74 dB (from 6.2 dB to 5.46 dB) in NF were achieved at 10 GHz and 13 GHz, respectively, for the SiGe HBT UWB LNA after the backside ICP dry etching. The excellent performances of the SiGe HBT UWB LNA with suspended inductors suggest that it is very suitable for UWB system applications. Besides, the BiCMOS‐process compatible backside ICP etching technique is very promising for BiCMOS integrated circuit (IC) applications. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2598–2601, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24691

Micromachined 50 GHz/60 GHz Phi filters by CMOS compatible ICP deep trench technology

AbstractMicromachined 50 and 60 GHz millimeter‐wave filters were implemented by using a 0.18 μm CMOS technology. The CMOS‐compatible inductively coupled‐plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filters completely, and so the substrate loss of the filters can be significantly reduced. The results show that 3.2, 2.6, and 2.1 dB improvements in S11, S21, and GAmax, respectively, are achieved for the 60 GHz filter after the backside ICP etching. Besides, for the 50 GHz filter, a 295.8% (from 9.6 to 38) improvement in Q‐factor of its inductors is achieved. These results show that the backside ICP etching is effective to reduce the substrate loss and parasitic capacitance in the millimeter‐wave frequency bands, and hence is very promising for millimeter‐wave CMOS RFIC applications. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3142–3146, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23915

Micromachined CMOS E‐band bandpass coplanar filters

AbstractIn this work, E‐band CMOS coplanar filters, whose initial design is made according to quasi‐ TEM‐approximation‐based analytical models, are implemented. To study the substrate effects, the CMOS‐compatible inductively coupled‐plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter completely. For the filter with top metal thickness of 0.93 μm after the backside ICP etching, the results show that the input matching bandwidth, i.e. S11 below −10 dB, moves from lower 39.8–81.4 GHz‐band to higher 55.9–94.1 GHz‐band, and the 3‐dB bandwidth of S21 moves from lower 43.5–76.3 GHz‐band to higher 54.5–93.3 GHz‐band. In addition, a 4.67 dB improvement [from −8.86 dB (at 58.5 GHz) to −4.19 dB (at 74.5 GHz)] in peak S21 was achieved. These results show that for the design of passive coplanar devices in the E‐band, the quasi‐TEM‐ approximation‐based analytical models can be used and the backside ICP etching is effective to reduce the substrate loss and parasitic capacitance. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3123–3125, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23873

An analysis of substrate effects on transmission‐lines for millimeter‐wave CMOS RFIC applications

AbstractA set of transmission lines (TLs) for millimeter‐wave (MMW) CMOS RFIC applications was implemented in a standard 0.18 μm CMOS technology and then postprocessed by CMOS‐compatible inductively‐coupled plasma (ICP) etching, which removed the silicon underneath the TLs completely. TL parameters such as characteristic impedance ZC, attenuation constant α, phase constant β, effective permittivity εeff, minimum noise figure (NFmin), parallel capacitance/conductance C/G, and series inductance/resistance L/R, as a function of frequency were extracted. It was found that α, εeff, NFmin, C, and G were greatly improved after silicon removal. The state‐of‐the‐art performances of the on‐chip TLs‐on‐air suggest that they are very suitable for application to realize ultralow‐noise MMW CMOS RFICs. Besides, the CMOS‐compatible backside ICP etching technique is very promising for MMW system‐on‐a‐chip applications. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 319–324, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23055

Ultralow-Loss and Broadband Micromachined Transmission Line Inductors for 30–60 GHz CMOS RFIC Applications

In this paper, for the first time, we demonstrate that ultralow-loss and broadband transmission line (TL) inductors can be obtained by using the CMOS-process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the TL inductors. The results show that a 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> , and a 0.404-dB (from 0.412 to 7.6times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) and a 1.082-dB (from 1.09 to 8.4times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) reduction in minimum noise figure NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> were achieved at 30 and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. The state-of-the-art performances of the on-chip TL inductors-on-air suggest that they are very suitable for application to realize ultralow-noise 30-60-GHz CMOS radio-frequency integrated circuit. In addition, the CMOS-process compatible backside ICP etching technique is very promising for system-on-a-chip applications.

A High-Performance Micromachined RF Monolithic Transformer With Optimized Pattern Ground Shields (OPGS) for UWB RFIC Applications

In this brief, we demonstrate that high-quality-factor and low-power-loss transformers can be obtained if the optimized pattern ground shields (OPGS) of polysilicon is adopted and the CMOS process-compatible backside inductively coupled-plasma (ICP) deep-trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 69.3% and a 253.6% increase in quality factor, a 10.5% and a 14% increase in magnetic-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Im</sub> ), a 17.2% and a 51.1% increase in maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.682- and a 1.79-dB reduction in minimum noise factor (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) were achieved at 5 and 8 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>

Characterization and Modeling of Pattern Ground Shield and Silicon-Substrate Effects on Radio-Frequency Monolithic Bifilar Transformers for Ultra-Wide Band Radio-Frequency Integrated Circuit Applications

In this paper, an analysis of the effects of pattern-ground-shield (PGS) and silicon-substrate on the performances of RF monolithic bifilar transformers are demonstrated. It was found that high-quality-factor and low-power-loss transformers can be obtained if the optimized PGS (OPGS) of polysilicon is adopted and the complementary metal–oxide–semiconductor (CMOS)-process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS (CPGS), which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 253.6% (from 3.79 to 13.4) increase in Q-factor, a 14% (from 0.7 to 0.798) increase in magnetic-coupling factor (kIm), a 51.1% (from 0.55 to 0.831) increase in maximum available power gain (GAmax), and a 1.79 dB (from 2.597 to 0.807) reduction in minimum noise factor (NFmin) were achieved at 8 GHz for a bifilar transformer with an overall dimension of 230×215 µm2.

An Analysis of Perfect-Magnetic-Coupling Ultra-Low-Loss Micromachined SMIS RF Transformers for RFIC Applications

Selective removal of the silicon underneath a set of single-turn multilayer interlaced stacked (SMIS) radio-frequency (RF) transformers with nearly perfect magnetic-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IM</sub> ~1) and high resistive-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Re</sub> ) is demonstrated. This process is based on the inductively coupled-plasma (ICP) deep trench technology. Improvement of 20.6 and 15.7 dB in isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) were achieved at 5.2 and 8 GHz, respectively, for a dummy open device after the backside ICP etching. Q-factor increases of 102% (from 4.96 to 10.03) and 23.2% (from 2.24 to 2.76), G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> increases of 11.8% (from 0.76 to 0.85) and 4.5% (from 0.88 to 0.92), and NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> decreases of 0.49 dB (from 1.22 to 0.73 dB) and 0.19 dB (from 0.55 to 0.36 dB) were achieved at 5.2 and 8 GHz, respectively, for an SMIS transformer with an overall dimension of 170times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> after the backside ICP etching. The G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.85 and 0.92 are both state-of-the-art results among all reported on-chip transformers. Furthermore, the reasons why the SMIS transformer exhibits better performances than the traditional bifilar and the traditional stacked transformer are explained. These results show that the micromachined SMIS transformers are very promising for RF integrated circuit applications

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> ) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after the backside ICP etching. The values of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.

Micromachined CMOS LNA and VCO by CMOS-compatible ICP deep trench technology

Selective removal of the silicon underneath the inductors in RF integrated circuits based on inductively coupled plasma (ICP) deep trench technology is demonstrated by a complementary metal-oxide-semiconductor (CMOS) 5-GHz low-noise amplifier (LNA) and a 4-GHz voltage-controlled oscillator (VCO). Design principles of a multistandard LNA with flat and low noise figures (NFs) within a specific frequency range are also presented. A 2-dB increase in peak gain (from 21 to 23 dB) and a 0.5-dB (from 2.28 to 1.78 dB) decrease in minimum NF are achieved in the LNA while a 3-dB suppression of phase noise is obtained in the VCO after the ICP backside dry etching. These results show that the CMOS-process-compatible backside ICP etching technique is very promising for system-on-a-chip applications.