Backside Gate Research Articles

(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology

This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon.

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing ${E}\,^{\prime }$ donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation.

Field Effect Modulation of Electrocatalytic Hydrogen Evolution at Back-Gated Two-Dimensional MoS2 Electrodes.

Electrocatalytic activity for hydrogen evolution at monolayer MoS2 electrodes can be enhanced by the application of an electric field normal to the electrode plane. The electric field is produced by a gate electrode lying underneath the MoS2 and separated from it by a dielectric. Application of a voltage to the back-side gate electrode while sweeping the MoS2 electrochemical potential in a conventional manner in 0.5 M H2SO4 results in up to a 140 mV reduction in overpotential for hydrogen evolution at current densities of 50 mA/cm2. Tafel analysis indicates that the exchange current density is correspondingly improved by a factor of four to 0.1 mA/cm2 as gate voltage is increased. Density functional theory calculations support a mechanism in which the higher hydrogen evolution activity is caused by gate-induced increase in the electronic charge on Mo metal centers adjacent to the S vacancies (the active sites), leading to enhanced Mo-H bond strengths. Overall, our findings indicate that the back-gated working electrode architecture is a convenient and versatile platform for investigating the connection between tunable electronic charge at active sites and overpotential for electrocatalytic processes on ultrathin electrode materials.

Dual-Gate MoS2FET With a Coplanar-Gate Engineering

A dual-gate multilayer MoS2 FET with a standard backside gate and a nonstandard coplanar top gate is demonstrated and analyzed. The special feature of this device is that the gate and MoS2 channel can be directly coupled on the same plane through the bottom-conducting Si substrate. The coplanar-gate MoS2 FET shows a good performance with a large ON–OFF ratio ( $I_{\mathrm{\scriptscriptstyle {ON/OFF}}}$ ) of $1.5\times 10^{4}$ , a small subthreshold swing ( $S$ ) of 0.13 V/decade, and a field-effect mobility ( $\mu $ ) of 0.69 cm2/Vs, respectively. Furthermore, a large $V_{\mathrm {{th}}}$ modulation ( $- 0.55\sim 6.4$ V) can be obtained in a dual-gate MoS2 FET by changing the coplanar-gate bias, which makes the device switch from depletion-mode to enhancement-mode operation, without affecting $\mu $ and $S$ , regardless of the coplanar-gate bias. In such a dual-gate MoS2 FET, both top and bottom gates can share the same SiO2 dielectric, and the deposition of source/drain/gate contact can be combined to a single step. A band diagram with the body effect theory is proposed to explain the device operation mechanism. The coplanar-gate MoS2 FET with its dual-gate operation and simple fabrication process can provide a good candidate for low-cost 2-D planar nanoelectronics and sensor applications.

High Performance Optical Modulator Based on Electro-Optic Polymer Filled Silicon Slot Photonic Crystal Waveguide

Silicon-organic hybrid integrated devices have emerging applications ranging from high-speed optical interconnects to photonic electromagnetic-field sensors. Silicon slot photonic crystal waveguides (PCWs) filled with electro-optic (EO) polymers combine the slow-light effect in PCWs with the high polarizability of EO polymers, which promises the realization of high-performance optical modulators. In this paper, a high-speed, power-efficient, low-dispersion, and compact optical modulator based on an EO polymer filled silicon slot PCW is presented. Lattice-shifted PCWs are utilized to engineer the photonic band diagram and thus enable an 8 nm-wide low-dispersion spectrum range, which is over an order of magnitude wider than that in modulators based on non-band-engineered PCWs and ring-resonators. A small voltage-length product of Vπ × L = 0.282 V × mm measured at 100 KHz is achieved by slow-light enhancement, corresponding to an unprecedented record-high effective in-device EO coefficient (r33) of 1230 pm/V among silicon-organic hybrid modulators. Excluding the slow-light effect, the actual in-device r33 is estimated to be 98 pm/V. By engineering the RC time constant via silicon doping and also utilizing a backside gate technique, the 3-dB modulation bandwidth of the device is measured to be 15 GHz. In addition, the RF power consumption of the modulator is estimated to be 24 mW at 10 GHz, and the estimated energy consumption for potential digital modulations is approximately 94.4 fJ/bit at 10 Gb/s.

Improvement of drain breakdown voltage with a back-side gate on AlGaN/GaN high electron mobility transistors

The effect of a back gate on the dc performance of AlGaN/GaN high electron mobility transistor was investigated. The back gate was fabricated directly under the device active area by etching off the Si substrate, AlN nucleation layer, and graded AlGaN transition layer and depositing Ni/Au-based gate metal on the exposed GaN buffer layer. The reverse bias gate leakage current decreased from 3.9 × 10−5 to 1.2 × 10−5 mA/mm by applying −10 V at the back gate. Because of the suppression of gate leakage current by the back gate, the drain on/off ratio improved from 1.8 × 105 to 1.2 × 106 and the subthreshold swing from 204 to 137 mV/dec. Moreover, the drain breakdown voltage could be improved by 40% when the back gate was biased at −25 V.

A Novel Backside Gate Structure to Improve Device Performance

AlGaN/GaN HEMTs have gained more attention recently because of the superior mobility (~1400 cm2/V-s) and high breakdown voltage. However, the reported breakdown voltage (~2000V at Lds=40µm) was still below GaN limit. The reason might be due to surface traps, defects in GaN buffer layer, etc. Methods to improve breakdown voltage include acceptor doping in buffer layer, insulator passivation or field plate over dielectric passivation. In this paper, we propose a new structure, which opened a via through the substrate as a backside gate and a field plate, and demonstrate the improvement of device performance such as transport characteristics and breakdown voltage. The HEMT structures consisted of a 25 nm AlGaN barrier layer, a 0.8 µm C doped GaN buffer layer, a 1.4µm AlGaN transition layer and a thin AlN nucleation layer on 300µm Si substrate. HEMT fabrication began with Ti/Al/Ni/Au Ohmic metallization and rapid thermal annealing in N2 at 825ºC. Isolation was accomplished by use of multiple energy N+ implantations. After implantation, the devices were passivated with 70-nm-thick SiNx by PECVD at 300ºC. Gate definition was achieved by patterning the gate and selectively removing the SiNx layer. The contact windows to the Ohmic contact pads were also opened simultaneously as defining the gate. After SiNx etching, wider gate patterns and Ohmic contact pads were opened. Ni/Au-based gate metallization was deposited on the gate and Ohmic contact pads simultaneously. The devices were then passivated with another 400-nm SiNx layer at 300ºC. The contact windows were opened by dry etching. The LDS was 4 µm. The LG was 0.45 and WG was 100 µm, respectively. There was an additional metal deposition for source field plate (FP). It was connected to the source and extended by 1 µm out over the gate to the gate-to-drain region. Above process flows are our standard process flow for reference. For our new structure, to drill via holes on the backside of the devices, the wafers were first polished to 150µm. Photoresist AZ9260 were used to pattern the via holes on the backside of the samples and aligned to the front side by Aligner MJB3. The high aspect ratio of the via holes were fabricated by BOSCH process. After forming via holes, Ti/Au was sputtered to form the backside gate (BG). Figure 1 showed effect of backside voltage (VBG) to drain I-V characteristics. As shown in Figure 1, the drain saturation current decreased and the channel resistance became higher after applying VBG at -10 V. Also, the drain current at pinch off region get decreased. This is due to the introduction of another depletion region from the backside of the device. In other words, the BG provided an additional control of the device, which made the device more robust. Figure 2 showed the transfer characteristics of device with and without applying VBG. As shown in Figure 2, both of the on current and off current became lower. Besides, the sub-threshold slope became steeper after applying -10 V at the BG, which meant better modulation of the device. Due to the better pinch off of the device, the breakdown voltage (VBD) was significantly improved. Table 1 showed the summary of the effect of VBG. As shown in TABLE 1, although IDS was slightly decreased, but the more reduction of gate current improved on/off ratio for one order, sub-threshold swing from 204 to 137 mV/dec, and VBD for 40%. These improvements were all achieved because of the backside gate. Besides applying VBG to improve VBD, the BG could be used as a FP, too. Studies have shown that FP can redistribute the electric field, and thus increase the VBD. In this study, we demonstrate the similar result. When connecting the BG to front-side gate, the VBD could be increased around 8 % as shown in Figure 3. When connecting the BG to front-side source, VBD didn’t have noticeable improvement. The reason that source FP didn’t have obvious effect in our study might be the existence of front-side FP. On the other hand, drain FP actually decrease the VBD. For drain FP, the backside FP was at positive bias. This positive bias along with the front-side positive bias would generate hot electrons and enhance the tunneling. In summary, VBD could be improved by simply connecting the backside gate to front-side gate. In conclusion, we demonstrate a new structure for AlGaN/GaN HEMT. This structure could improve the on/off ratio, sub-threshold swing, and breakdown voltage. It is worth to see if it could improve short channel effect, self-heating effect, or current collapse. Figure 1

A Novel Backside Gate Structure to Improve Device Performance

A novel structure with backside gate was proposed in this study. The effect of backside gate to the device performance including DC performance and breakdown voltage was investigated. When the back-side gate was biased at -25V, the leakage current could be suppressed to one order lower. As a result, the subthreshold swing (SS) could be improved from 240 to 137 mV/dec. Most important of all, the off-state drain breakdown voltage could be increased by 40%. If the back-side gate is connected to the front-side gate, which could be viewed as a back-side gate field plate structure, the off-state drain breakdown voltage could be improved by 7%

Extraction of Trap Densities in TFTs using C-V Characteristics

TFTs have been widely applied to FPDs. Amorphous-Si TFTs are representatively used for large-size televisions, poly-Si TFTs are utilized for mobile smartphones, oxide-semiconductor TFTs are newcomers promising for next-generation displays, and organic-semiconductor TFTs are possibilities expected for future printed electronics. Although many researchers investigate device structures and fabrication processes, device characterizations are also important in order to develop these TFTs. In this presentation, we will introduce the device characterizations based on low-f C-V methods and numerical analysis and results acquired for various kinds of TFTs.Trap states are some of the main determinants of TFT performances. Although there exist many evaluation techniques for the trap states such as optical and crystallographical techniques, electrical techniques are most effective because TFTs are employed as electrical devices and only electrically active trap states during actual operations can be extracted using the electrical techniques. Furthermore, general techniques available for any kinds of these TFTs are preferable. As such techniques, we are developing low-f C-V methods conjunct with numerical analysis. The unique merit is that the charge densities and therefore trap densities are directly counted and no mobility models are necessary unlike the conventional electrical techniques.First, low-f C-V characteristics are measured. Since the measurement f must be extremely low to ensure the quasi-static condition, the gate width must be very wide to make the capacitance large and measurement error small. If CMOS technology can be used, p/i/n-type TFTs are more favorable to make both electron and hole transportations smooth. In addition, the measurement system must be highly customized. Frequency dependence of C-V characteristics of a p/i/n-type poly-Si TFT is shown in Fig. 2. Since this frequency dependence is mainly due to the running time of the free carriers from the source-drain regions to the entire channel layer, the gate length must not be too long. Here, since the C-V characteristics almost agree when f is 1 Hz and 0.7 Hz, the C-V characteristic reaches the quasi-static condition when f is 1 Hz.Next, surface potential (Φs) is calculated from the low-f C-V characteristic by applying Q = CV to the gate insulator. Energy band along the vertical direction in TFTs is shown in Fig. 3. Q=Ci(Vgs-Φs) dΦs/dVgs=1-(dQ/dVgs)/Ci=1-Cg(s+d)/Ci Φs=∫(1-Cg(s+d)/Ci)dVgsAs a result, Φsas well as its gradient at the semiconductor interface ((dΦs/dx)i) are calculated as functions of Vgs.Afterward, we have to select a proper approximation for the spatial distribution of the trap states. In the cases of amorphous-Si TFTs, SPC poly-Si TFTs having poor film qualities, some oxide-semiconductor TFTs, and organic-semiconductor TFTs, trap states in the semiconductor films are dominant. In the cases of ELC poly-Si TFTs and some oxide-semiconductor TFTs, trap states at the semiconductor-insulator interfaces are dominant. On the other hand, in the case of SPC poly-Si TFTs having excellent film qualities, these trap states are comparable and should be simultaneously considered. In the case of ELC poly-Si TFTs, trap states at the front and back interfaces and grain boundaries should be simultaneously considered. Selecting a proper approximation, using physical equations such as Poisson equations, carrier density equations, and Gauss's law, executing numerical analysis, and fitting the calculated Φsand (dΦs/dx)i to those calculated from the low-f C-V characteristics, trap densities can be extracted. Sometimes, more complicated analyses are executed by combining other electrical characteristics such as backside C-V characteristics of TFTs equipping backside gate terminals and I-V characteristics.Trap densities in various kinds of TFTs with a reference of crystal-Si MOSFETs are shown in Fig. 4 as examples of extracting the trap densities. First of all, the total numbers of the trap states are still higher for all TFTs than crystal-Si MOSFETs. Amorphous-Si TFT: The trap states consist of the deep states and tail states, and Gaussian states at a certain energy level often appear owing to the dangling bond. SPC poly-Si TFT: in the case of a well-fabricated SPC poly-Si TFT, the TFT characteristics are influenced by both the in-film trap densities (Dfi) owing to the micro twins principly formed during the SPC and interface trap densities (Dit) dependent on the surface treatment processes. ELC poly-Si TFT: We think that the front side and backside Dit are mainly owing to the dangling bonds, whereas the grain-boundary trap densities (Dgb) owing to the bond distortion. Amorphous-InGaZnO TFTs: Dfi just below Ec can be reduced using post annealing, which seriously influence the TFT characteristics. Poly-ZnO TFT: Dfi is strongly dependent on the process conditions such as oxygen partial pressure during sputtering of ZnO films.

Electrical Transport and Field-Effect Transistors Using Inkjet-Printed SWCNT Films Having Different Functional Side Groups

The electrical properties of random networks of single-wall carbon nanotubes (SWNTs) obtained by inkjet printing are studied. Water-based stable inks of functionalized SWNTs (carboxylic acid, amide, poly(ethylene glycol), and polyaminobenzene sulfonic acid) were prepared and applied to inkjet deposit microscopic patterns of nanotube films on lithographically defined silicon chips with a back-side gate arrangement. Source-drain transfer characteristics and gate-effect measurements confirm the important role of the chemical functional groups in the electrical behavior of carbon nanotube networks. Considerable nonlinear transport in conjunction with a high channel current on/off ratio of approximately 70 was observed with poly(ethylene glycol)-functionalized nanotubes. The positive temperature coefficient of channel resistance shows the nonmetallic behavior of the inkjet-printed films. Other inkjet-printed field-effect transistors using carboxyl-functionalized nanotubes as source, drain, and gate electrodes, poly(ethylene glycol)-functionalized nanotubes as the channel, and poly(ethylene glycol) as the gate dielectric were also tested and characterized.

Scalable 3-D Fin-Like Poly-Si TFT and Its Nonvolatile Memory Application

In this paper, we extensively investigated the structure and electrical characteristics of an n-type poly-Si thin-film transistor with a novel 3D fin-like channel. Further, owing to the high-quality thin film in the channel, an experimental device with a nonvolatile (NV) memory structure for system integration on panel or embedded memory applications is successfully demonstrated for the first time. By following the previously reported method and by improving the process conditions, the final fin-like channel shows a real 3D profile and a maximum aspect ratio of 3.5:1 with a minimum average width equal to 135 nm after an excimer laser annealing on a unique prepatterned amorphous silicon channel. The high-level dc characteristics, such as carrier's field-effect mobility up to 289 cm2 /V.s, subthreshold slope below 190 mV/dec, ON-OFF current ratio greater than 5 x 106, etc., reveal the effect of film quality and the advantage of the gate-all-around structure on the device's performance; moreover, it also indicates one potential scaling method for this technology. By applying a special program/erase (P/E) mode with electron injection/expulsion from the backside gate electrode, the NV memory structure in this channel demonstrates reasonable P/E characteristics, threshold voltage shifting of 1.41 V at | Vg = 12 V, pulse time = 1 ms, and acceptable reliability.

Thin film transistors of single-walled carbon nanotubes grown directly on glasssubstrates

We report a transistor of randomly networked single-walled carbon nanotubeson a glass substrate. The carbon nanotube networks acting as the activecomponents of the thin film transistor were selectively formed on the transistorchannel areas that were previously patterned with catalysts to avoid theetching process for isolating nanotubes. The nanotube density was more than50 µm−2, which is much larger than the percolation threshold. Transistors were successfullyfabricated with a conducting and transparent ZnO for the back-side gate and the top-sidegate. This allows the transparent electronics or suggests thin film applications of nanotubesfor future opto-electronics.

Fabrication of Carbon Nanotube Field-Effect Transistors with Metal and Semiconductor Electrodes

ABSTRACTCarbon nanotube field-effect transistors (CNTFETs) were fabricated with metal material (gold) and semiconductor material (bismuth telluride) as the source and drain materials. Highly-purified HiPCO-grown single-walled carbon nanotubes (CNTs) from Carbon Nanotechnologies, Inc. (CNI) were used for the fabrication of CNTFETs. The single-walled carbon nanotubes were ultrasonically dispersed in toluene and dimethylformamide (DMF) with trifluoroacetic acid (TFA), as co-solvent. Dielectrophoresis (DEP) method was used to deposit, align, and assemble carbon nanotubes (CNTs) to bridge the gap between the source and drain of CNTFETs to form the channel. The structure of CNTFET is similar to a conventional field-effect transistor with substrate acting as a back-side gate. Electron-beam evaporation was used to deposit gold and bismuth telluride thin films. Microfabrication techniques such as photolithography, e-beam lithography, and lift-off process were used to define and fabricate the source, drain, and gate of CNTFETs. The gap between the source and drain varied from 800 nm to 3 µm. The drain-source current (IDS) of the fabricated CNTFETs versus the drain-source voltage (VDS) and the gate voltage (VG) was characterized. It was found that in the case of gold (Au) electrodes, the IV curves of CNTFETs clearly show behavior of the CNT (metallic or semiconducting) aligned across the source and drain of CNTFETs, while in the case of bismuth telluride (Bi2Te3) electrodes, the I-V curves are less dependent on the type of CNTs (metallic or semiconducting). The developed carbon nanotube field-effect transistors (CNTFETs) can be a good candidate for the application of nanoelectronics and integrated circuits with a high mobility and fast switching.

Porous Silicon on Insulator: A New Approach to Fabricate Porous Silicon Based Optoelectronic Devices

A new fabrication technique of laterally anodized porous silicon is presented. This technique, when applied to bulk silicon wafers, generates a uniform pattern of light emitting porous silicon with high quality smooth interfaces with the surrounding silicon. Additional improvement is achieved by using silicon-on-insulator wafers. In this case, a backside gate contact allows electrical control of the anodization process and a fabrication of porous silicon on insulator structures. It is shown that this technique is capable of producing optical waveguide structures with smooth interfaces and high confinement of the optical mode to the porous silicon layers. Optical and structural characterizations of the porous silicon on insulator structure are presented demonstrating uniform, low loss optical waveguides.

Effects of the gate bias on the activation energies of the fractional quantum hall effect

The temperature dependence of the resistivity minima of the 1 3 and 2 3 effect in the fractional quantum Hall effect has been measured for GaAs/AlGaAs heterostructures with a backside gate. The μB dependence of the activation energies has been obtained by controlling the electron density and the mobility applying a bias on the backside gate. The results indicate that the activation energies are enhanced by a positive bias and are reduced by a negative bias. The magnetic field dependence of the activation energies obtained using the gate bias cannot be free from this effect.

Second Activation Energy in the Fractional Quantum Hall Effect

The temperature dependence of the resistivity minima of the 2/3 effect in the fractional quantum Hall effect has been measured for a GaAs/AlGaAs heterostructure with a backside gate. The results at the highest negative gate bias have shown a single activated conduction. The systematic change of the temperature dependence controlled by the gate bias indicates that this activation energy does not correspond to the excitation energy of the quasi-particles, that is, there is a second activation process in the fractional quantum Hall effect.

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.

A study of intersubband scattering in GaAs/Al xGa 1− xAs heterostructures by means of a parallel magnetic field

We demonstrate the influence of intersubband scattering in GaAs/AlGaAs heterostructures by means of a parallel magnetic field. For samples with a carrier density such that the second subband is lightly populated, the mobility can be increased by about 50% due to the suppression of intersubband scattering, when the subband separation is increased by a strong magnetic field parallel to the interface. This gives rise to a strong negative magnetoresistance. The onset of this negative magnetoresistance can be shifted by the application of a back-side gate voltage which varies the Fermi energy.