Backside Condition Research Articles

Effects of Implant Temperature, Backside Contamination and Scribe Lines on Room Temperature Photoluminescence Measurements on Silicon

To investigate the effect of implantation temperature on the damage to a Si lattice, room temperature photoluminescence (PL) spectra were measured from highly-channeled MeV 11B+ implanted Si wafers with different implant temperatures (25 °C and 450 °C) after annealing at 950 °C for 3 min in N2. Small pieces from the wafers were used for PL characterization. The implanted Si wafer piece at the elevated temperature resulted in higher overall PL intensity under both excitation wavelengths suggesting lesser lattice damage than the Si wafer implanted at room temperature. Unexpectedly large PL intensity variations were observed from PL area mapping of both wafer pieces. In addition, strange behaviors of localized PL intensity variations, with opposite trends between 670 nm and 827 nm excitation PL measurements were observed near the scribe lines and sample number markings on the backside. The PL intensity was increased under 670 nm excitation while it was decreased under 827 nm excitation. Possible reasons for this strange behavior were discussed based on experimental results and analysis. PL measurement is verified to be very sensitive to the surface condition, interface, bulk and backside conditions of the Si. For reliable PL measurement, backside contamination and scratches, such as scribe lines, should be avoided.

Characterization of coplanar strip lines on dielectric boards for RF and microwave applications

We report the characterization of coplanar strip (CPS) transmission lines on dielectric boards at millimeter-wave frequency up to 40 GHz. The CPS line was analyzed and simulated using computer-aided design tools. Many CPS lines were built on RT/Duroid board and the measured attenuation is as low as 0.8 dB/cm at 30 GHz. CPS lines of various electrode width and width-to-gap ratios were measured to obtain key design guidelines. The CPS line has both the signal and ground electrodes on the front surface of the board. In contrast to the microstrip line, the CSP line does not include the backside of the board as a part of the transmission line. Thus, the backside can be left open as dielectric or metallized. The backside condition can affect the wave propagation if it is too close to the electrodes. We simulated and measured the attenuation coefficient, line impedance, and electrical field distributions for different backside conditions. Our results clearly indicate that the CPS line is an attractive transmission line on the board level in millimeter electromagnetic waves applications. Its applications can be extended to microwave and millimeter-wave integrated circuits. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.

Controllable periodic structures on silicon wafer by CO 2 laser irradiation

Laser-induced periodic microstructures on the silicon substrate have been studied using a pulsed CO 2 laser under the backside conditions. The microstructures are formed with periodic parallel fringes and circular fringes on the front surface of silicon substrate, when the backside of which is coated with a thin layer of paints or Au. The parallel fringes have a period around 2 μm with fringe orientation in parallel with the laser polarization direction. The spacing of the circular fringes is less than 2 μm. The fringe period and depth can be controlled by varying the laser parameters. The microstructures are independent on the laser pulses, therefore, are re-writable. The periodic structures are considered to be formed by the thermal capillary wave effect and the laser-induced periodic surface structure effect—the LIPSS effect, during the material melting and re-solidification processes. The laser absorption is assumed to be induced by the increase of free carrier concentration, and the thermal energy resulting from the laser interaction with the backside coating materials.

Evaluation of Applied Materials' Rapid Thermal Processor using Sematech Methodologies for 0.25 m Technology Thermal Applications-Part II

AbstractUnder a joint development contract with Applied Materials (AMAT) and Texas Instruments (TI), SEMATECH undertook a project (Joint Development Project J100) with a goal of delivering a cost effective, technically advanced Rapid Thermal Processor (RTP). The RTP tool was specified to meet the present and future manufacturing needs of SEMATECH's member companies. The J100 results contained here will focus on the temperature and control performance of the AMAT RTP tool. The J100 results on the temperature measurement and control performance of AMAT's RTP tool using bare backside monitor wafers were presented in part I. In actual manufacturing environments the backside conditions of wafers are not consistent which causes temperature variations during rapid thermal processing. In this experiment, boron monitor wafers with varying backside conditions were used to test the uniformity, repeatability, and stability of the tool. The wafer backside films were fabricated using predictions from emissivity models and were subsequently verified by experimental techniques. In addition, perturbation experiments utilizing boron and arsenic implanted wafers demonstrated a high degree of localized temperature control across the wafers. A 3-sigma temperature variation ranging from 3.0 °C (for wafers with similar backside films) to 6.0 °C (for wafers with varying backside films) was found for all wafers processed during this evaluation. The perturbation experiments, which included a forced temperature offset of two degrees at one of the wafer temperature sensors, resulted in a noticeable change in sheet resistance across the wafer.

Temperature Monitoring by Ripple Pyrometry in Rapid Thermal Processing

AbstractCurrent trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.

Quantitative Infrared Spectroscopy of Interstitial Oxygen in Silicon Wafers Using Multivariate Calibration

A PLS multivariate calibration method is used to create a reliable means for the determination of the interstitial oxygen content in silicon wafers. The multivariate calibration, derived from silicon standards with various backside treatments, provides similar precision measurement capability when compared to peak area calibration curves established from individual backside treatments. In this case, the significant advantage of the multivariate calibration is that a single calibration can yield interstitial oxygen results that correlate favorably with vendor values over a wide range (20 to 40 ppma), regardless of the backside condition of the wafers.