Back-gate Contact Research Articles

Sub-nanometer manipulation of multiple nanoparticles by non-uniformly back-gated graphene sheet/strips

Taking advantage of a non-uniformly biased graphene sheet, a novel electrically reconfigurable platform for sub-nanometer manipulation of nanoparticles (NPs) is proposed. Numerical simulations show that using a well-designed V-shaped back-gate contact, the graphene sheet can function as an inhomogeneous graphene strip with electrically tunable edges. Under certain conditions, localized surface plasmons (LSP) can be coupled to the induced edges, realizing strongly confined and enhanced edge-coupled LSP hot spots (trapping sites). Tuning the gate voltage tunes the induced edges and consequently the trapping sites with sub-nanometer resolution. Moreover, we demonstrate that using graphene strips (instead of a graphene sheet), the proposed structure can trap NPs in three dimensions and manipulate them in 2D. We believe this platform can open up exciting possibilities for future integrated reconfigurable lab-on-a-chip devices to accurately control the trapping sites, manipulate, route, and deliver NPs.

(Invited) Dual-Gate TFT for Chemical Detection

Field effect transistors possesses many advantages for chemical detection. As their electrical characteristics strongly depend on electrical charges located on their surface, they are able to measure with good sensitivity and very precisely any variation of charges concentration of the surrounded media. They can be easily integrated, are low-cost and provide a rapid and reliable result. The main application developed here is the pH measurement. In this case, the gate contact is removed and replaced by a liquid polarized by a reference electrode, leading to the ISFET technology. Those structures can also be developed by using a thin-film technology. The technology we developed is based on LPCVD polysilicon, silicon oxide and nitride deposited by CVD. The sensitivity of ISFET or ISTFT is limited by Nernst equation, but can be enhanced by using dual-gate structures. In this technology, capacitive enhancement can be optimized by choosing specific thicknesses and materials for back and top gates. In this case, the sensitivity enhancement is theoretically given by the ratio of the top gate capacitance to the back-gate capacitance. This technology has been developed also by using thin-film transistors from polysilicon material. Several structures have been developed in order to obtain good electrical performances for field-effect transistors, as low threshold voltage and good electrical characterization for back and top gates. Those characteristics are controlled by a good choice of insulator, and a thickness optimization. Transistors are characterized with different polarizations; in back-gate, top-gate and dual-gate operating modes. Capacitive enhancement in determined for the different cases and compared to theory. Transistors are then used for chemical detection, especially with measurement of pH. ISFET is already highly used for pH measurement, but its sensitivity is limited to 59 mV/pH. By using a dual-gate structure, this sensitivity can be substantially enhanced. The developed structures, based on previous studies of dual-gate TFTs, includes a back-gate contact, and an integrated electrode at the surface for the top-gate liquid polarization. Threshold voltage are measured and optimized. A slight doping of the active layer induces a decrease of the threshold voltage, necessary in the case of measurement in liquids. Sensitivities for pH measurement are compared with theory and show the capacitance enhancement. Figure 1

The rise of silicene

Silicene is the silicon counterpart of graphene, that is, it consists of a single layer of Si atoms arranged in a hexagonal network. This new two-dimensional material, first predicted by theory, has been recently grown on different metallic surfaces.1, 2, 3 An obvious advantage of silicene (over graphene) for nanoelectronic applications is its better compatibility and expected integration with the existing Si nanotechnology platform. A new breakthrough on this material has been recently reported by Tao et al.,4 who have successfully fabricated the first silicene-based field effect transistors (FETs) operating at room temperature. Their success relies on the development of a layer transfer process, called ‘silicene-encapsulated delamination with native electrodes’ (SEDNE). This innovative process includes the following key steps: (1) epitaxial growth of silicene on Ag(111) thin films grown on mica substrates; (2) Al2O3 in situ encapsulation of the silicene layer, followed by its delamination transfer on a p++Si/SiO2 substrate; and (3) subsequent Ag source/drain contact formation by e-beam lithography. A resulting silicene-based FET, with the p++Si substrate used as a back-gate contact, is shown in Figure 1a.

Backgating effect in III–V MESFET’s: A physical model

The backgating (sidegating) effect in III–V MESFET’s devices is analyzed through the modelisation of a Metal (Schottky barrier)–N (channel)–SI (Semi Insulating)–N+ (back-gate contact) structure. Numerical and analytical results, using the drift–diffusion charge transport model, show that along the applied voltage range associated with backgating: (i) quasi space charge neutrality across most of the bulk SI layer and (ii) quasi Boltzmann equilibrium for the free electron across the reverse biased N (channel)–SI contact prevail for GaAs (SI) or InP (SI). The circumstances under which a negative bias applied on the back-gate (N+) contact will either develop across the reverse biased N–SI contact (strong backgating) or across the SI layer (negligible backgating) are described by means of a simple analytical relation as a function of the deep level parameters values. The electric field dependence of the carrier mobility (Gunn effect) produces a backgating effect with a threshold voltage. The presence of a low lifetime, buffer layer, at the N–SI interface is shown to strongly reduce it.

Dielectric thickness dependence of capacitive behavior in graphene deposited on silicon dioxide

Scanning capacitance microscopy (SCM) is used to probe on nanoscale the capacitive behavior of graphene deposited on a SiO2∕Si n+ substrate (with SiO2 thickness of 300 or 100nm). The SCM tip provides the contact on graphene, while the Si n+ substrate acts as the backgate contact in the graphene/SiO2∕Si capacitor. The authors studied the screening by the graphene two-dimensional electron gas on the modulating potential applied between the backgate and the SCM tip. In particular, they determined the effect of the oxide thickness on the lateral distribution (i.e., screening length) and the density of the screening charge in graphene. Experimental results indicate that thinner oxide leads to higher screening charge density in the graphene sheet and to higher effectively biased area on graphene. This correspondingly increases the total capacitance (Ctot) of the graphene/SiO2∕Si capacitor. We evaluated the dependence on the dielectric thickness of the classical metal-oxide-semiconductor (MOS) capacitance (CMOS) and of the quantum capacitance (Cq) contributions to Ctot.

Electrochemical Growth of InSb Nanowires and Report of a Single Nanowire Field Effect Transistor

InSb nanowires with high crystalline properties are synthesized with a diameter of 200 nm via direct current electrodeposition method inside the nanochannels of anodic alumina membranes. For the first time, the characteristics of field effect transistors based on InSb nanowires synthesized via electrochemistry is presented. A single InSb nanowire is used as a channel with gold source and drain contacts. A P ++ silicon substrate is used as the back-gate contact. Both nanowire synthesis and device fabrication are performed at room temperature and nanowire hole mobility is measured to be 57 cm 2 V -1 S -1 suggesting high structural quality of the as-grown InSb nanowires.

Weak localization in back-gated Si/Si0.7Ge0.3quantum-well wires fabricated by reactive ion etching

The electronic properties of Si/${\mathrm{Si}}_{0.7}$${\mathrm{Ge}}_{0.3}$ quantum-well wires fabricated by reactive ion etching are investigated. The width of the nonconducting layer produced by the dry-etch damage and surface depletion is determined by plotting the conductance vs wire width for wires with lithographic widths ranging from 0.10 to 1.0 \ensuremath{\mu}m. The combined width of the so-called ``dead layers'' on each edge of the wire is determined to be as small as 0.13\ifmmode\pm\else\textpm\fi{}0.01 \ensuremath{\mu}m. Quantum interference effects are studied in wires with lithographic widths of W=0.23 \ensuremath{\mu}m. One-dimensional (1D) weak localization is evident in these wires at T=1.3 K in the form of a pronounced negative magnetoresistance for |B|\ensuremath{\leqslant}0.3 T. A back-gate contact is used to study the electron-transport properties in the wires, as a function of the electron sheet concentration, ${\mathit{n}}_{\mathit{s}}$. The data have been fitted to the 1D theory of weak localization, and indicate that the inelastic mean free path ${\mathit{L}}_{\mathrm{\ensuremath{\varphi}}}$ increases from 0.2 to 1.2 \ensuremath{\mu}m as ${\mathit{n}}_{\mathit{s}}$ is increased from 4.2\ifmmode\times\else\texttimes\fi{}${10}^{11}$ to 5.9\ifmmode\times\else\texttimes\fi{}${10}^{11}$ ${\mathrm{cm}}^{\mathrm{\ensuremath{-}}2}$ at T=1.3 K. \textcopyright{} 1996 The American Physical Society.

The dependence of AlGaAs/GaAs MODFET isolation on material and device structure

Investigations on the dependence of AlGaAs/GaAs Modulation Doped Field Effect Transistor (MODFET) isolation on device and epitaxial material structure are reported. For single heterojunction devices with thick (1 μm) undoped GaAs buffer layers, the backgating characteristics are found to be independent of device structure and backgate-MODFET spacing. In the case of thin GaAs buffer layer structures ( ⩽2000 A ̊ ), a considerable backgating dependence on device structure is observed. For a 2000 Å buffer layer and a particular device structure, the drain-source current is found to drop by only ∼ 3% when −10 V is applied to a backgate contact located 2 μm from the MODFET. The excellent isolation provided by this device and material structure is attractive for fabrication of high packing density integrated circuits with reduced material growth times.

The electrical and optical properties of a four-terminal top back gate FET

A novel four-terminal device, the top back gate FET (TBGFET) grown by MBE is fabricated. A n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> Sn-doped GaAs buried-contact layer is grown on Cr-doped SI first, and an undoped Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</inf> - Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</inf> As insulating layer and Sn-doped GaAs channel are grown subsequently. Nonselective mesa etch is used for device isolation and selective etch is adopted to open the back-gate contact window. TBGFET Works as a MESFET and MISFET with a common channel, but can be separately controlled by the top gate and the back gate. We can adjust the transconductance and current level at room temperature as we wish by properly applying negative bias to the back gate or top gate. The top-gate threshold voltag <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{t} = -1.6</tex> V and back-gate threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bt</inf> from -0.5 to -10 V are obtained under different insulator thickness and trap density. If a proper criterion is satisfied, either top-gate threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> or back-gate threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bt</inf> can be independently chosen without influencing each other. The decoupling of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bt</inf> are well explained by the Lampert's law of the trap-fill-limited carrier injection in semi-insulator. The device interaction with light is also investigated. It is foUnd that the back-gate threshold voltage shift as well as the conduction current enhancement is caused principally by photon-induced detrapping in the semi-insulated AlGaAs layer. Photon generated e-h pairs in the device channel play a minor role either in current enhancement or in back-gate threshold voltage shift. Both <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Delta V_{bt}</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Delta I_{ds}</tex> are increased with the light intensity and tend to saturate at some fixed values. Based on the above properties, a number of applications of TBGFET in digital and microwave circuit are proposed.