Back End Of Line Stack Research Articles

Microcracking in On-Chip Interconnect Stacks: FEM Simulation and Concept for Fatigue Test

The semiconductor industry is continuing the scaling down of both device and on-chip interconnect features, for performance and economic reasons. This trend has implications for the design of guard ring structures, i.e. metallic non-functional structures in the back-end-of-line (BEoL) stack designed to be efficient to stop microcracks. In this work, we present a sample design for an in situ experiment to study mechanical degradation and failure mechanisms of crack stop structures in the BEoL stack, to ensure the mechanical robustness of microchips for future technology nodes. Additional finite element method (FEM) simulations provide supplementary understanding of the crack kinetics. To examine the effects of mechanical loading on crack stop elements of the BEoL stack, a novel sample geometry for an in situ fatigue experiment using x-ray microscopy was developed. The x-ray microscope (ZEISS Xradia 800 Ultra) enables high-resolution imaging of the 3D-patterned sample structures and defects such as microcracks. The tailored sample geometry allows the application of a tensile load to a BEoL specimen by a lever mechanism. The feasibility of the sample design is shown by mode-I loading of a pure interconnect sample. Post-mortem analysis by scanning electron microscopy (SEM), confirming planar microcrack propagation from the notch through the dielectric layer with small deflections of the crack path near cone shaped copper vias. FEM simulations focusing on the stress-strain fields around a crack tip indicate the beginning of copper plasticity as major mechanism starting the redirection of cracks due to resulting material compression in front of the obstacle.

Adhesion experiments on Cu-Damascene processed interconnect structures for mode III loading

This study presents a novel approach of micromechanical interfacial testing in loading mode III. The interfaces beneath single copper interconnect structures are investigated. The method is based on lateral nanoindentation experiments, utilized to probe customized copper torsion structures manufactured by the Dual Damascene process. Thus, the test structures resemble product-like length-scales and properties. For the investigation of interface properties, the experimental load-displacement data were reviewed. Two different interfaces occurring in Back End of Line (BEoL) structures are probed: Copper to Ta/Ta-N barrier as well as Copper to Si-N. SEM images and FIB cross-sections are performed, validating the delamination of the targeted interface. While the first interface shows a very high strength and cannot be delaminated by the here presented experiments, the latter one was brought to delamination in mode III several times. The tests yielded reproducible load-displacement data, the load at delamination for the interface Copper to Si-N was measured to be 130 ± 40 μN. A simple analytical approximation for the maximum shear stresses applied in mode III at the interface of interest is provided. The proposed testing approach is able to reproducibly manufacture and test large quantities of the reality like test structures, while avoiding time-consuming FIB based preparation routines. This can help to evaluate the interface properties in modern BEoL stacks and could lead to simulation based design improvements.

BEoL stack robustness investigations utilizing Cu-pillar immobilization and micromechanical loading methods

Under harsh application conditions in fields such as aerospace or automotive, it is crucial that the mechanical robustness of microchip components is ensured at any time. To obtain this, thorough and highly specialized testing approaches have to be deployed already in the design phase. The general strategy of these approaches is to induce (thermo-)mechanical load to a given system or component under well controlled conditions and assess the resulting effects. The testing methods should emulate the mechanical application conditions as closely as possible to identify the most damage prone areas of the system and to obtain an understanding of the occurring damage processes. In this work, the development and deployment of two different testing methods to evaluate mechanical BEoL (Back end of Line) stack robustness by inducing micromechanical load to superjacent Cu-pillars are introduced. In flip chip applications, Cu-pillars are immobilized by a solder connection as well as underfill material. Compared to previously developed methods, it was attempted to realize mechanical scenarios which are closer to assembly or application conditions. Therefore, the methods presented in this work can be regarded as subsequent developments of e.g. the Cu-pillar shear-off approach presented in Silomon et al. (2021). The details are discussed in more depth in Silomon et al. (2022). Specifically, a mechanical immobilization approach utilizing an indenter tip with a cavity was developed as well as a soldering approach utilizing a Cu indenter tip as a soldering bolt and a landing pad simultaneously. The approaches were deployed on a high-end microchip sample which has been introduced and investigated in Silomon et al. (2021).Two different mechanical loading conditions were emulated utilizing the developed approaches. These conditions are relevant at different points in the life cycle of a microchip and could not be induced utilizing previously developed methods. Oscillating load as an emulation of thermal expansion and contraction or vibration (application conditions) as well as tensile loading as an emulation of assembly conditions were induced. Applying mechanical load to individual Cu-pillars utilizing the different methods enabled the determination of the failure conditions and subsequent analysis led to the identification of the respective damage mode. Additionally, sub-critical experiments utilizing AE (acoustic emission) signal monitoring as a damage indicator were conducted to determine the exact location of damage initiation. This was achieved by subsequent damage assessment measurements utilizing optical microscopy, nXCT as well as SEM/FIB analyses. Applying this workflow, it was possible to describe the damage modes as well as to identify the most damage prone areas for the specific loading conditions induced by the two different developed mechanical loading methods.

Crack identification and evaluation in BEoL stacks of two different samples utilizing acoustic emission testing and nano X-ray computed tomography

A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with copper pillar bumps is used. In a second step, the validity of the approach is also shown for a second sample manufactured in 22 nm technology and the experimental results are compared. To inflict damage to the BEoL stack of the respective semiconductor device, external forces are applied to the copper pillars (Cu-pillars) by shear loading using a tribo-indenter system. An acoustic emission (AE) detection sensor is attached to the sample to measure acoustic waves during the shear experiment as an indication for damage. The damage progression in the BEoL stack is extremely fast, hence details can't be resolved anymore with the piezo sensors of the tribo-indenter. However, due to the much higher temporal resolution, AE measurements give a more precise insight into the damage process. The resulting damages are imaged using nano X-ray computed tomography (nXCT) as well as scanning electron microscopy (SEM). The results provide a better understanding of the origin and the propagation of damages in the BEoL stack.

Standardized Heat Spreader Design for Passive Cooling of Interconnects in the BEOL of ICs

The back-end components of integrated circuits (ICs) are susceptible to self-heating deteriorating effects due to the microscale interconnects carrying large current densities, and thus require innovative passive cooling strategies. This article investigates the cooling effect of the high conductivity metallization (MET) fill that is used in conjunction with the chemical mechanical planarization (CMP) process. Thermal simulation models are developed for a three-level back end of line (BEOL) stack and then validated experimentally using high-resolution thermal imaging. A coupled approach is used to optimize the numerical model and fully characterize the BEOL embedded passive cooling solution. Results indicate that stricter thermal constraints are present for devices higher in the BEOL stack and exhibit the highest cooling potential from the use of CMP fill in the underlying MET layers. As a thermal improvement strategy for such thermally critical interconnects, a CMP fill-based cooling solution is presented by modifying the fill pattern in order to maximize heat dissipation within the BEOL. The resulting heat spreader (HS) design achieved up to 30% reduction in temperature for 10- $\mu \text{m}$ -wide interconnects and can reach 43% for narrower interconnects. The gained cooling makes it possible to extend the activation limits of interconnects by 15% and 25%, respectively. The experimentally validated HS simulation model is used to conduct parametric analysis for a range of interconnect dimensions with an eye on standardizing the HS design within the BEOL stage of ICs.

Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements

Abstract This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility

In advanced technology nodes, correctly choosing among available back-end-of-line (BEOL) stack options is important to meet stringent design quality of results requirements. However, it is nontrivial to evaluate BEOL stack options since the routing outcomes highly depend on the input design (e.g., netlist, placement, etc.). In this paper, we propose a systematic framework to measure routing capacity of a BEOL stack as well as inherent capability of routers. Based on our experimental results, we observe consistent results across mesh-like placement and placements from various placers. Also, our proposed framework enables new insights into important questions regarding BEOL stack options. Using our framework, we further study the relation between the routing hotspot size and routing failure empirically. Lastly, we present an analytical study based on exponentiation of a Markov transition matrix about the impact of design size on routing failure.

In-situ X-ray Microscopy of Crack-Propagation to Study Fracture Mechanics of On-Chip Interconnect Structures

ABSTRACTChip-package interaction (CPI) and the related thermomechanical stress in microchips increase the risk of failure in on-chip interconnect stacks, caused by delamination along Cu/dielectrics interfaces (adhesive failure) and fracture in dielectrics (cohesive failure). High-resolution transmission X-ray microscopy (TXM) is a unique technique to image crack propagation in on-chip interconnect stacks. The visualization of crack evolution in Cu/low-k Backend-of-Line (BEoL) structures is demonstrated using an experimental setup which combines high-resolution X-ray imaging with mechanical loading. The application of an indenter manipulator at the TXM beamline of the synchrotron radiation source BESSY II provides an unprecedented level of details on the fracture behavior of microchips. This in-situ experiment allows to identify the weakest layers and interfaces and to evaluate the robustness of the BEoL stack against CPI.

A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line

Abstract This paper describes a systematic approach to the identification of primary contributing factors to the Chip Package Interaction (CPI) risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The strategy includes modeling at bump and package level, gathering experimental data on blanket dielectric back end of line (BEoL) films, collecting data on wafer material with a complete BEoL stack, and finally using readouts on the package level. Advanced measurement methods generate data on the wafer level to achieve fast turn-around times. These methods include: (i) Dual-Cantilever Beam (DCB) test, (ii) Modified Edge Lift-off Test (MELT), (iii) Single Pillar Shear Test (SPST) and (iv) Bump Assisted BEoL Stability Indentation (BABSI) tests. The paper describes the methodology to gather data on the wafer level with a complete BEoL metallization stack that assesses the BEoL integrity. Furthermore, the package level thermomechanical modeling approach is discussed. The model has been used to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow processes. Silicon design-related factors in the BEoL that contribute to the risk for CPI related failures were investigated and options to reduce the CPI risk are discussed. Finally the paper reveals package level qualification data flip-chip CSP and wafer level packaging Fan-In for advanced technology nodes.

Characterization of critical conditions for fracture during wafer testing by FEM and experiments

In this work, we investigate finite element models of an imprinting scenario of a needle into a thin metallic film together with corresponding experiments in order to analyze the critical conditions that lead to brittle fracture in Back End Of Line (BEOL) bond pad stacks during wafer testing. We investigate the elastic-plastic material properties of the individual BEOL material layers and propose a plasticity law in terms of a stress-strain curve for the aluminum layer. Instrumented indentation testing is undertaken in order to reproduce the conditions that BEOL pad stacks are exposed to during wafer testing. Along with this, physical failure analysis reveals the dominant failure modes in the BEOL stack after indentation. We investigate the influence of silicon oxide and copper layers embedded below the first silicon oxide layer on failure. Finally, we provide an approach value for the fracture strength of the silicon oxide film that shows good agreement with previous literature data.

Shear test on hard coated flip-chip bumps to measure back end of the line stack reliability

Introduction of ultra-low κ (ULK) material into advanced back end of line (BEOL) stacks has improved the electrical performance of the flip-chip microelectronic packages. However, the integration of the brittle and porous ULK materials presents several mechanical reliability challenges due to chip-package interaction effects. One of the primary failure modes in a organic flip-chip microelectronic package is delamination of interlayer dielectric (ILD) layers. Thermo-mechanical stresses that arise at the end of flip-chip assembly process can be high enough to cause fracture of the ILD layers in the vicinity of a solder bump. It has been observed from experiments that two bumps subjected to apparently same amount of thermo-mechanical stresses and same process history can exhibit difference in failure pattern. Current numerical models nor micro- scale interfacial fracture characterization experiments such as double cantilever beam (DCB) or four-point bend (FPB) tests are not capable of predicting such a failure. Such a behavior is possible only if the adhesion strength of the ILD layers are not constant but varies spatially from bump to bump. The difference in adhesion strength between adjacent bumps can be attributed to the difference in trace pattern layout or via distribution. In order to understand the failure at the bump level that is sensitive to capture differences in local trace patterns, microscale test techniques need to be developed.The focus of this work is to demonstrate a new reliable microscale test technique performed using nano-indenter to measure the mechanical reliability of BEOL stacks. A high-load spherical head is used to apply a known displacement on a solder bump coated with a ceramic. The force initial increases and suddenly drops indicating failure. Cross-sections of the tested bumps clearly indicate crack propagating through the BEOL stack while the coated bump remains intact. Since the forces subjected on the bump during the test is similar to the forces subjected on the bump during flip-chip assembly, the critical force can be used as a measure of fracture strength of the BEOL stack. The results from the test indicate that the critical force varies from bump to bump and the results are repeatable. Furthermore, finite-element model of the test is developed. The failure of the ILD layers is simulated using cohesive zone (CZ) elements and the mixed-mode traction-separation parameters required to characterize the CZ elements are extracted from macro-scale test techniques like DCB and FPB tests. The force-displacement (P-Δ) plot from the model mimics the experiment and predicts the average value of the critical force observed in experiment.

Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100nm near the transistors and 1000nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers.This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data.

Advanced experimental back-end-of-line (BEOL) stability test: Measurements and simulations

Chip–package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations.

Stress analyses of high spatial resolution on TSV and BEoL structures

Knowledge and control of local stress development in Back-End-of-Line (BEoL) stacks and nearby Through Silicon Vias (TSVs) in advanced 3D integrated devices is a key to their thermo-mechanical reliability. The paper presents a combined simulation/measurement approach to evaluate stresses generated in the result of the TSV and BEoL stack manufacturing and 3D bonding processes. Stress measurement methods of high spatial resolution capability (microRaman and Focused Ion Beam (FIB) based stress release techniques) are used to obtain stress data from real components as manufactured. Finite Element Analysis (FEA) allows a more accurate interpretation of measurements results as well as a subsequent comprehensive analysis of failure behaviour. The paper gives an introduction to the applied local stress measurement on advanced multi-layer systems and 3D integration components referring to the state-of-art capabilities and limitations. The need of experimental stress data generation is illustrated on FEA examples. Illustration is given for FEA applications on 3D IC integration components currently lacking appropriate residual stress input for an assumed initial state.