Average Power Tracking Research Articles

Study and implementation of a novel high‐efficiency piezoelectric energy harvesting circuit

SummaryThis paper proposes a self‐powered SSHI piezoelectric energy extraction circuit combined with Modified FOCV‐MPPT technology, which analyzes the electrical characteristics of S‐SSHI operation. The paper demonstrates that the determination of the optimal operating state of S‐SSHI can be determined independently of the open‐circuit voltage. Based on the key parameters obtained from the theoretical analysis, the FOCV‐MPPT strategy is modified, and the corresponding functional circuit is designed. This strategy serves as an intermediate stage between S‐SSHI and the load, addressing the dependence of S‐SSHI output power on the load while avoiding the power supply interruption issue of the traditional FOCV‐MPPT strategy. In addition, the higher output power provided by S‐SSHI improves the utilization of MPPT technology. The correctness of the investigations is verified through the simulation and experiments. By using self‐powered S‐SSHI, the proposed circuit increases the output power of PEH by a factor of 2.46. In the open‐circuit voltage range of 2–7 V, the average maximum power tracking efficiency achieved 90.1%. The maximum tracking efficiency can reach 98%.

Robust Cadence and Power Tracking on a Switched FES Cycle With an Unknown Electromechanical Delay

Functional electrical stimulation (FES) is commonly used to facilitate cycling tasks for people with lower-limb movement disorders. In this work, FES and motor controllers are designed to track a desired power and cadence, respectively, and a Lyapunov-based switched systems analysis is performed to guarantee uniformly ultimately bounded power tracking and global exponential cadence tracking for a switched, delayed, nonlinear, and uncertain FES-cycling system. A unique challenge in this problem is that there is an unknown time-varying input delay to produce force, and a different unknown time-varying residual input delay where force is still produced after stimulation is removed. These delays impact the dwell-time conditions that dictate stimulation timing, and if not properly accounted for can lead to undesired effects such as antagonistic muscles exerting force at the same time or potential instabilities. The proposed controllers were validated by experimental analysis of four participants with neurological conditions (NCs) and five able-bodied participants, and yielded average power and cadence tracking errors of 0.01 ± 0.09 W and −0.05 ± 0.65 revolutions per minute (RPM), respectively, for the able-bodied participants and 0.01 ± 1.11 W and −0.07 ± 1.17 RPM, respectively, for the participants with NCs.

Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End

This article presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on long-term evolution (LTE) and 5G bands. The designed fully switched-mode SM consists of a fast switching buck converter and a slow switching buck converter, and it achieves 88.2% peak efficiency and a low receiver (RX) band noise of −140 dBm/Hz at the SM output. The fully switched-mode SM tracks the envelope of LTE 5-/10-/20-MHz signals with the average switching frequencies of 50/70/120 MHz, respectively. The ET-PA measured using the fully switched-mode SM and LTE band-3 power amplifier module integrated duplexer (PAMiD) saves the dc power consumption of 320 mW at a 23-dBm output power compared to an average power tracking (APT)-PA. The designed 5G new radio (NR) SM consisting of a class-AB linear amplifier (LA) and an interleaved three-level buck–boost converter provides a 160-MHz 3-dB bandwidth to track the envelope of a 100-MHz NR signal. The measured peak SM efficiency is 84.1% at a 3.53-W output power. The measured ET-PA with 5G NR SM and 5G n77 PAMiD achieves an ACLR of −36.9 dBc at a 27.45-dBm output power with a 6-dB peak-to-average-power ratio DFT-spread-OFDM NR 100-MHz quadrature phase shift keying (QPSK) signal. It saves the dc power consumption of 950 mW at a 27-dBm output power compared to APT-PA. An optimal RF power amplifier (RF-PA) supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual-transmission requirements of E-UTRAN new radio dual-connectivity (EN-DC) and 5G 100-MHz ET operation. The fully switched-mode SM is implemented in a 130-nm CMOS process, and the die size is 4.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The 5G NR SM is implemented in a 90-nm CMOS process, and the die size is 6.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An Envelope Tracking Supply Modulator Utilizing a GaN-Based Integrated Four-Phase Switching Converter and Average Power Tracking-Based Switch Sizing With 85.7% Efficiency for 5G NR Power Amplifier

This article proposes a supply modulator (SM) that uses high switching frequency gallium-nitride (GaN) devices to achieve a four-phase fast step-down converter for the fast-tracking ability of the envelope tracking (ET). The ET signal is reshaped to generate an average power tracking (APT)-based signal to control the size of GaN switches to further increase light-load efficiency due to reduced switching loss. Moreover, a high-bandwidth and low-loss linear amplifier (LA) is used to supply the power amplifier (PA) to sufficiently provide fast-tracking speed for 5th generation (5G) NR ET. At a power of 3.5 W for 5G mobile phones, the peak efficiency that is tested with NR −130 MHz in the ET mode is as high as 85.7% over a wide load range.

Torque and cadence tracking in functional electrical stimulation induced cycling using passivity-based spatial repetitive learning control

Due to the inherent periodic nature of cycling tasks, iterative and repetitive learning controllers are well motivated for rehabilitative cycling. Motorized functional electrical stimulation induced cycling is a rehabilitation treatment where multiple lower-limb muscle groups are activated jointly with an electric motor to achieve cycling objectives such as speed (cadence) and torque tracking. This paper examines torque tracking accomplished by the stimulation of six lower-limb muscles via a novel spatial repetitive learning control and cadence regulation by an electric motor using a sliding-mode controller. A desired torque trajectory is constructed based on the rider’s kinematic efficiency, which is a function of the crank position. The learning controller takes advantage of the periodicity of the desired torque trajectory to provide a feedforward input to the stimulated muscles. A passivity-based analysis is developed to ensure stability of the torque and cadence closed-loop error systems. The muscle learning and electric motor controllers were implemented in real-time during cycling experiments on five able-bodied individuals and three participants with movement disorders. The combined average cadence tracking error was 0.01±1.20 RPM for a 50 RPM trajectory and the combined average power tracking error was 1.78±1.25 W for a peak power of 10 W.

CMOS-Compatible MESFETs for High Power RF Integrated Circuits

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a 45-nm silicon-on-insulator CMOS technology available from Global Foundries. MESFETs with gate lengths of 200 nm show good manufacturability with well-controlled run-to-run variations. The DC and RF performance of devices with different drain access lengths are compared to illustrate the design trades between high breakdown voltage and high frequency operation. Two applications of the MESFETs for RF integrated circuit design are presented. The first demonstrates integrated n-channel MOSFET-MESFET cascode amplifiers that combine the enhanced voltage operation of the MESFET with the high frequency capability of the scaled MOSFET. The resulting small-signal amplifiers demonstrate cut-off frequencies of 50 GHz when operated with supply voltages of 6 V, significantly higher than the nominal 1 V breakdown voltage of the CMOS transistors. The second application demonstrates a watt-level MESFET power amplifier integrated with a CMOS current steering digital-to-analog converter (DAC). The MESFET serves as the RF output device, while the 4-bit CMOS DAC enables average power tracking. Both examples demonstrate the design flexibility enabled by the CMOS-compatible MESFETs.

High-Efficiency Stacked Power Amplifier IC With 23% Fractional Bandwidth for Average Power Tracking Application

This paper presents a two-stage stacked power amplifier integrated circuit (PAIC) for broadband and high efficiency using a 2-μm InGap/GaAs HBT process with a second-harmonic control circuit and a bias-switching circuit for an average power tracking (APT) application. For APT operation, active bias circuits with a bias switching circuit for the stacked stage were proposed. A simple L-section matching network with a second-harmonic termination circuit was adopted for broad bandwidth and high efficiency. The frequency-independent power and efficiency contours for fundamental and second-harmonic frequency band were extracted at the current-source plane of the transistor. The implemented two-stage PAIC was evaluated using a long-term evolution signal with a peak-to-average power ratio (PAPR) of 7.5 dB and a signal bandwidth of 10 MHz. From 1.55 to 1.95 GHz, the power amplifier exhibited average output power ranging from 27.4 to 28.5 dBm, a power gain of more than 28.6 dB, and a power-added efficiency (PAE) of 36.5 to 41.2% at an ACLR of -30 dBc. At an average output power back-off of 5 dB, the PAE improved to 29.5% with APT using an external buck-boost dc-dc converter, while it was 18.7% without APT.

Design of Boosted Supply Modulator With Reverse Current Protection for Wide Battery Range in Envelope Tracking Operation

This paper presents a hybrid supply modulator (SM) including a buck-boost (BB) converter, which has wide battery operating range for cellular envelope tracking (ET) applications. The proposed SM supports both ET and average power tracking (APT) mode depending on the power amplifier (PA) output power level. The output voltage swing of SM is boosted up to 4.5 V by the integrated BB converter as a supply of a linear amplifier. The dynamic-controlled BB output increases ET operating range, whose efficiency is higher than that of APT, by scaling down the supply voltage of the linear amplifier according to the PA output power level. A selective supply voltage of a switching amplifier and a reverse current sensing circuit are employed to prevent the reverse current through the power inductor of the switching amplifier. The proposed automatic current ratio controller between the linear amplifier and the switching amplifier provides the robust performance against the battery voltage variation of 3.2–4.6 V. A programmable bias current of the class-AB output buffer and a programmable hysteretic comparator are employed to achieve the optimum efficiency and bandwidth depending on the operating signal bandwidth. Optimal control for low signal bandwidth applications such as voice over Long-Term Evolution (LTE) with the selective notch filter provides the maximum efficiency of 88.2% with −135 dBm/Hz output noise. The proposed SM supports the LTE 20-MHz envelope signal with 78% efficiency at 800-mW output. Adapting the designed SM to frequency-division duplex Band3 radio frequency PA, the implemented ET-PA achieves the power added efficiency of 41.6% at 27-dBm PA output power while achieving −40 dBc of E-UTRA ACLR and −137 dBm/Hz of receiver band noise. The chip is implemented in the 0.13- $\mu \text{m}$ CMOS process, and the die size is 5 mm2.

Highly Linear mm-Wave CMOS Power Amplifier

A Ka-band highly linear power amplifier (PA) is implemented in 28-nm bulk CMOS technology. Using a deep class-AB PA topology with appropriate harmonic control circuit, highly linear and efficient PAs are designed at millimeter-wave band. This PA architecture provides a linear PA operation close to the saturated power. Also elaborated harmonic tuning and neutralization techniques are used to further improve the transistor gain and stability. A two-stack PA is designed for higher gain and output power than a common source (CS) PA. Additionally, average power tracking (APT) is applied to further reduce the power consumption at a low power operation and, hence, extend battery life. Both the PAs are tested with two different signals at 28.5 GHz; they are fully loaded long-term evolution (LTE) signal with 16-quadrature amplitude modulation (QAM), a 7.5-dB peak-to-average power ratio (PAPR), and a 20-MHz bandwidth (BW), and a wireless LAN (WLAN) signal with 64-QAM, a 10.8-dB PAPR, and an 80-MHz BW. The CS/two-stack PAs achieve power-added efficiency (PAE) of 27%/25%, error vector magnitude (EVM) of 5.17%/3.19%, and adjacent channel leakage ratio (ACLR $_{\mathrm{ E-UTRA}}$ ) of −33/−33 dBc, respectively, with an average output power of 11/14.6 dBm for the LTE signal. For the WLAN signal, the CS/2-stack PAs achieve the PAE of 16.5%/17.3%, and an EVM of 4.27%/4.21%, respectively, at an average output power of 6.8/11 dBm.

A − 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter

This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 $\Omega $ resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is −137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is −124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18- $\mu\mbox{m}$ CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.

Analysis of Average Power Tracking Doherty Power Amplifier

An average power tracking (APT) Doherty power amplifier (PA) is analyzed in terms of its biasing voltage condition, efficiency, and output power. And the drain and gate bias voltages are optimized for operation at different output power conditions. The Doherty power amplifier is designed using 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The bias voltages are controlled for each average power level(42.9 dBm, 39.9 dBm, 37 dBm). The measured drain efficiencies and gains are 53.2%, 12.8 dB at 42.9 dBm and 54.3%, 11.2 dB at 39.9 dBm and 53.4%, 9.1 dB at 37 dBm for a 10 MHz LTE signal with a 6.5 dB PAPR. This result demonstrates that the Doherty PA can be reconfigured for different average output powers using the bias voltage control method.

An Average Power Tracking Method for Wideband Highly Nonlinear Power Amplifiers

An accurate average power tracking method is presented to track and compensate the fluctuation of power amplifier (PA) output during updates of digital predistorter. Firstly, joint distortion probability distribution (JDPD) of the predistorter input signal and PA compression state is presented to extract the average power gain fluctuation related to the nonlinearity of the PA. The accurate PA compression state is extracted by linear-zone-reposition technique. Then, the average power gain fluctuation related to PA memory is obtained assisted by the predistortion model. The PA output power fluctuation is well controlled through the proposed method. Results from experiments show that the performance of DPD improves at least 3 dB for long time experiments when the proposed method is used for wideband highly nonlinear PA.

Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a 0.18-㎜ CMOS process for the 1.75 ㎓ band. For the 16-QAM LTE signal with a peakto-average power ratio of 7.3 ㏈ and a bandwidth of 5 ㎒, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 ㏈, and an adjacent channel leakage power ratio of -30 ㏈c at an average output power of 22 ㏈m, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 ㏈m.

On the Robustness of Digital Predistortion Function Synthesis and Average Power Tracking for Highly Nonlinear Power Amplifiers

In this paper, a comprehensive study of the robustness of the digital predistortion function synthesis is presented. This study covers two aspects: the processing of the power amplifier (PA) input and output measured data intended for the extraction of the corresponding predistortion function, and the optimal setting of the predistorter's small-signal gain to adaptively track the average power variation between the input and output of the pre-distorter. First, the accuracy of the polynomial curve fitting and the lookup table's scheme in mimicking the measured AM/AM and AM/PM characteristics of the PA is investigated. To address the high dispersion of coefficients of the polynomial function, which limits the order that can be implemented and the fitting capabilities, a pre-processing technique is proposed. Second, the fitted PA curves are used to investigate the effects of the small-signal gain of the predistortion function on the linearization performance. An automated average power tracking technique is introduced in order to maintain a unit average gain of the predistorter. The measured spectra at the output of the amplifier show an additional 12-dBc improvement in the output spectrum regrowth.