Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End

Abstract

This article presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on long-term evolution (LTE) and 5G bands. The designed fully switched-mode SM consists of a fast switching buck converter and a slow switching buck converter, and it achieves 88.2% peak efficiency and a low receiver (RX) band noise of −140 dBm/Hz at the SM output. The fully switched-mode SM tracks the envelope of LTE 5-/10-/20-MHz signals with the average switching frequencies of 50/70/120 MHz, respectively. The ET-PA measured using the fully switched-mode SM and LTE band-3 power amplifier module integrated duplexer (PAMiD) saves the dc power consumption of 320 mW at a 23-dBm output power compared to an average power tracking (APT)-PA. The designed 5G new radio (NR) SM consisting of a class-AB linear amplifier (LA) and an interleaved three-level buck–boost converter provides a 160-MHz 3-dB bandwidth to track the envelope of a 100-MHz NR signal. The measured peak SM efficiency is 84.1% at a 3.53-W output power. The measured ET-PA with 5G NR SM and 5G n77 PAMiD achieves an ACLR of −36.9 dBc at a 27.45-dBm output power with a 6-dB peak-to-average-power ratio DFT-spread-OFDM NR 100-MHz quadrature phase shift keying (QPSK) signal. It saves the dc power consumption of 950 mW at a 27-dBm output power compared to APT-PA. An optimal RF power amplifier (RF-PA) supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual-transmission requirements of E-UTRAN new radio dual-connectivity (EN-DC) and 5G 100-MHz ET operation. The fully switched-mode SM is implemented in a 130-nm CMOS process, and the die size is 4.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The 5G NR SM is implemented in a 90-nm CMOS process, and the die size is 6.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .