Avalanche Ruggedness Research Articles

Review and analysis of SiC MOSFETs’ ruggedness and reliability

SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Investigation of the avalanche ruggedness of SiC MPS diodes under repetitive unclamped-inductive-switching stress

State of the art freewheeling diodes are connected antiparallel with a switch like IGBT or MOSFET and for latter also with the internal body diode. The diodes have to be rugged enough to overcome temporary overvoltage and overcurrent conditions during transient operation. SiC merged pin Schottky (MPS) diodes are one of the superior contenders and thus it is essential to make investigations under high avalanche energy. In this work, an avalanche ruggedness of 20 A/1.2 kV SiC MPS diodes was investigated far beyond the specified maximum ratings of the device under unclamped inductive switching (UIS) measurement. The function of avalanche energy versus applied inductance was investigated under single event avalanche stress. The reliability under high repetitive avalanche energy was studied in detail. A forward voltage drift, change in the Schottky junction voltage and increase in the leakage current was observed after the high repetitive avalanche stress far beyond the safe operating area. Detailed failure analysis was made, focusing on the degradation of the metallization and possible stacking faults (SFs) in the SiC bulk. Furthermore, the temperature was determined as a function of the blocking voltage during avalanche stress.

Safe Operation of Maximum Temperature for Planar Gate SiC Mosfet under Avalanche Stress Shock

Avalanche capability is one of the most significant ruggedness concerns. In this paper, avalanche capability of 1200V 80mΩ CREE SiC MOSFET characterizing planar gate structure is assessed under unclamped inductive switching test with various loads (3.6mH, 1.1mH, 0.3mH). Through similar maximum withstanding avalanche energy for the three loads and failure behavior, the heat induced failure can be determined, even though very different maximum avalanche peak currents I av,pk and avalanche time t av. The increasing avalanche energy generates heat to rise device temperature until the maximum temperature approaches the metal system on the surface of SiC material. The maximum safe operation temperature for planar SiC MOSFET is determined by the metal melting point. The avalanche ruggedness of the SiC MOSFET provides related information to application design. The results can also help understand ultimate failure cause of avalanche shock and improve the ruggedness of device.

Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current ( ${I}_{\text {AV}}$ ) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 $000~\mu \text{m}$ .

Investigation on single pulse avalanche failure of SiC MOSFET and Si IGBT

In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

Avalanche ruggedness of parallel SiC power MOSFETs

The aim of this paper is to investigate the impact of electro-thermal device parameter spread on the avalanche ruggedness of parallel silicon carbide (SiC) power MOSFETs representative of multi-chip layout within an integrated power module. The tests were conducted on second generation 1200 V, 36 A–80 mΩ rated devices. Different temperature-dependent electrical parameters were identified and measured for a number of devices. The influence of spread in measured parameters was investigated experimentally during avalanche breakdown transient switching events and important findings have been highlighted.

Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules

This paper provides an insight into the operational robustness of commercially available SiC MOSFET power modules, during short-circuit (SC) and unclamped inductive switching (UIS) test environments. A set of five different power modules from three vendors rated from 1.2–1.7kV and with various current ratings have been evaluated, where the possible failure mechanisms that cause the breakdown of the modules have been addressed. The SC pulse duration of the modules was gradually increased until the failure occurred. A critical short circuit energy in the order of 4.0–8.0J was observed at a supply voltage of 800V and a pulse duration of 4.0μs. At lower supply voltage of 500V, all modules survived until 10.0μs. One of the modules, rated at 1.7kV, survived SC tests at voltages up to 1000V for a pulse duration of 4μs, but failed when the supply voltage was increased to 1100V. Prior to failure, a gate-source voltage drop has been recorded, which is associated with a high G-S leakage current. The main failure mechanism, however, is the thermal runaway which leads the devices into avalanche breakdown mode. During the UIS tests, multiple samples from the three vendors of the power modules failed. The failure of the modules was always caused by the external diode connected in parallel with the MOSFETs. One of the modules from the same vendor which does not have external diode and another module from a different vendor with external diode survived the UIS tests under nominal test conditions.

1200 V FS‐IGBT with electric field modulation layer to improve trade‐off between avalanche ruggedness and on‐state voltage drop

In this Letter, a novel 1200 V FS- insulated gate bipolar transistors (IGBT) is proposed to improve the trade-off between avalanche ruggedness and on-state voltage drop. The proposed IGBT features the high doping and thin n-layer under trench gates and we call it the electric field modulation layer (EFM layer). Under the avalanche condition, the EFM layer can form the sharp electric filed distribution in the EFM layer and the avalanche multiplication is constrained in the thin EFM layer. The difference between the holes and electrons due to the avalanche multiplication effect at the emitter side of the IGBT is minished. Therefore, the negative difference resistance in the avalanche I–V curve caused by the difference between the holes and electrons is eliminated. As a consequence, the avalanche ruggedness of the EFM-IGBT is improved. In the on-state, the high doping EFM layer can store the carriers and the on-state voltage drop of the EFM-IGBT is reduced to 1.48 V at 200 A/cm2. Finally, the EFM-IGBT improves the trade-off between avalanche ruggedness and on-state voltage drop.

Silicon Carbide Schottky Rectifiers with Improved Avalanche Ruggedness

Silicon carbide Schottky-barrier diode (SBD) rectifiers have been manufactured with low on-state voltages, high surge currents and high avalanche ruggedness. Non-destructive unclamped inductive switching currents of 188 A (mean) are achieved for the 1200 V 15 A rectifier. Very tight distribution of maximum sustained UIS current is confirmed. We relate improved avalanche ruggedness to bulk avalanche breakdown and show the breakdown pattern of the new Schottky rectifier being the same type as that for the p-n diode.

On the avalanche ruggedness of optimized termination structure for 600 V punch-through IGBTs

In this paper, the current paths in avalanche conditions of a Floating Field Ring (FFR) termination for a Punch-Through (PT) Insulated Gate Bipolar Transistor (IGBT) are analyzed. The design of the termination region is achieved with two different optimization techniques, and both static and dynamic electrical behavior are analyzed by means of 2D TCAD simulations, up to high current density levels. A comprehensive analysis of the Unclamped Inductive Switching (UIS) operation of the proposed terminations is carried-out with electro-thermal simulations. Although the behavior of both structures at low current levels is different, results show the same current crowding effect at the main junction for high current levels, resulting in a reduced conduction area of the overall termination, hence, of the avalanche reliability. Finally, experimental confirmation of filamentary current conduction during UIS test are detected on 600V commercial devices by means of transient infrared thermography.

Avalanche Capability of Vertical GaN p-n Junctions on Bulk GaN Substrates

Inductive avalanche test results presented in this letter demonstrate that GaN p-n diodes can sustain single-pulse and repetitive inductive avalanche currents. The 0.36-mm2 vertical GaN p-n diodes can sustain single-pulse avalanche currents as high as 10 A. The safe zone of the single-pulse avalanche current is limited by peak pulse power and energy deposited in the device. The temperature-dependent behavior of the breakdown voltage and the reverse-voltage at onset of avalanche has a positive temperature coefficient. Repetitive avalanche ruggedness testing was performed by applying $10^{\mathrm {5}}$ pulses at 5-kHz frequency with increasing repetitive stress current. Based on a population of 63 devices, the incremental failure rate under repetitive avalanche current increases with increasing avalanche current. The devices that survive the step stress test sustain no parametric drift under repetitive avalanche.

Effect of the Collector Design on the IGBT Avalanche Ruggedness: A Comparative Analysis Between Punch-Through and Field-Stop Devices

In this paper, we investigate the effect of collector design on the onset and the extension of the negative differential resistance (NDR) region that develops in the blocking curves of field-stop (FS) and punch-through (PT) insulated gate bipolar transistors. Differences on the NDR extension and on its temperature behavior for the PT structures with respect to the FS ones are found, and their dependence from the collector design is explained. Subsequently, the dynamic filamentary current conduction mechanism is studied by means of 2-D electrothermal simulations on a wide area structure with many elementary cells on PT and FS devices. The differences between the two structures in terms of filament movement and its influence on the max temperature of the hot spot are then demonstrated to adversely affect the ruggedness of PT devices compared with the FS ones.

Reliability studies of vertical GaN devices based on bulk GaN substrates

There is great interest in wide band-gap semiconductor devices and most recently in vertical GaN structures for power electronic applications. In this paper initial reliability studies of vertical p–n diodes and vertical junction field effect transistors fabricated on pseudo bulk low defect density (104 to 106cm−2) GaN substrates are discussed. Homoepitaxial MOCVD growth of GaN on its native substrate and being able to control the doping in the drift layers in GaN has allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40μm and net carrier electron concentrations of 2×1015 to 2×1016cm−3. This parameter range is suitable for applications requiring breakdown voltages of 1200V to 5kV with a proper edge termination strategy. Measured devices demonstrate power device figure of merit of differential specific on-resistance (Rsp) of 2.8mΩ-cm2 for a breakdown voltage of 4.1kV. The improvement in the substrate quality over the last few years has resulted in the fabrication of diodes with areas as large as 16mm2, with breakdown voltages exceeding 1200V, and pulsed (100μs) currents of 100–400A. Furthermore, impact ionization based avalanche breakdown has been demonstrated in GaN for the first time due to the high quality of the crystals grown on the native substrates. With these key demonstrations firmly in place, it is necessary to evaluate the reliability performance of vertical GaN devices on bulk GaN substrates. The results of high temperature reverse bias (HTRB), high temperature operating life (HTOL), temperature humidity bias (THB), temperature cycling (TC), and inductive avalanche ruggedness tests conducted on vertical GaN devices packaged in standard power packages are reported. It is observed that fundamental failure mechanisms are almost always traced back to the starting substrate material quality, substrate miscut angle, and surface morphology post epi growth. No observation of Rds drift is made for vertical diodes or transistors fabricated on bulk GaN substrates under the stress conditions mentioned above once a suitable back metal and die attach process is developed.

Uniform Luminescence at Breakdown in 4H-SiC 4°-Off (0001) p–n Diodes Terminated With an Asymmetrically Spaced Floating-Field Ring

Conventional floating-field rings, which are used to reduce the peak electric field at the periphery of power devices, cause nonuniform avalanche multiplication when applied to planar junctions formed on 4H-SiC substrates misoriented from (0001) toward $[{ 11}{\overline {2}}0]$ . Accordingly, a novel asymmetrically spaced floating-field ring (AS-FFR) was applied to 4H-SiC 4°-off (0001) p–n diodes and found to be effective against such nonuniform avalanche multiplication; that is, luminescence at breakdown was nearly uniform when the spacing between the edge of the anode and the inner edge of the AS-FFR was 2.0 ${{\mu }}\text{m}$ in the [ $\overline { 1}{\,}\overline {1}20$ ] direction and 1.5 ${{\mu }}\text{m}$ in the $[{11}{\overline {2}}0]$ direction. This result should contribute to exploring the possibility of 4H-SiC power devices with higher avalanche ruggedness.

Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation Silicon Carbide (SiC) power MOSFETs under Unclamped Inductive Switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their ageing under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development.

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low-voltage trench power n-type MOSFETs (nMOSFETs) is assessed. Trench power nMOSFETs with 20- and 30-V breakdown voltage ratings in TO-220 packages have been fabricated and subjected to over 100 million cycles of repetitive UIS with different avalanche currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AV</sub> at a mounting base temperature T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MB</sub> of 150°C. Impact ionization during avalanche conduction in the channel causes hot-hole injection into the gate dielectric, which results in a reduction of the threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> , as the number of avalanche cycles N increases. The experimental data reveal a power-law relationship between the change in the threshold voltage ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> and N. The results show that the power-law prefactor is directly proportional to the avalanche current. After 100 million cycles, it was observed in the 20-V rated MOSFETs that the power-law prefactor increased by 30% when I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AV</sub> was increased from 160 to 225 A, thereby approximating a linear relationship. A stable subthreshold slope with avalanche cycling indicates that interface trap generation may not be an active degradation mechanism. The impact of the cell pitch on avalanche ruggedness is also investigated by testing 2.5- and 4- m cell-pitch 30-V rated MOSFETs. Measurements showed that the power-law prefactor reduced by 40% when the cell pitch was reduced by 37.5%. The improved V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> stability with the smaller cell-pitch MOSFETs is attributed to a lower avalanche current per unit cell resulting in less hot-hole injection and, hence, smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> shift. The 2.5-m cell-pitch MOSFETs also show 25% improved on -state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSON</sub> , better R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSON</sub> stability, and 20% less subthreshold slope compared with the 4-m cell-pitch MOSFETs, although with 100% higher initial I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</sub> and less I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</sub> stability with avalanche cycling. These results are important for manufacturers of automotive MOSFETs where multiple avalanche occurrences over the lifetime of the MOSFET are expected.

Avalanche Capability of Unipolar SiC Diodes: A Feature for Ruggedness and Reliability Improvement

SiC Diodes in the 300 to 1200V range have steadily increased their market penetration in the last 7 years. Especially the 600V SiC diodes are a nearly mandatory device for further increase of power density in modern switch mode power supplies. Those devices entered the market from the high end side due to the still significant higher costs in comparison with conventional fast Si diodes. On the other hand, these high end markets like server or telecom power supplies also require very high reliability of the devices used. In previous papers we showed, that Merged-PN-Schottky (MPS) diodes can be designed for avalanche ruggedness [1,2]. In this paper we will describe, how this feature supports overall reliability improvement. Addditionally, we will show, how a conventional SiC Schottky diode without MPS structure can be modified in order to achieve stable avalanche breakdown in combination with strong reliability improvement.