Auxiliary Pair Research Articles

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators’ performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier’s differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator’s speed by more than 10%.

Bilateral fault-tolerant qudit teleportation in multi-hop quantum networks

In this paper, we present one general fault-tolerant multi-hop teleportation scheme for arbitrary unknown qudit system, exploring a strategy for distilling high-dimensional EPR pairs within the operational errors channel, where the introduced auxiliary pairs don’t have to be in high-fidelity. These errors can be detectable and traceable in quantum networks, promising that the accumulation of the operational errors can be rectified by the final receiver during the teleportation, avoiding the error correction implemented by the intermediate nodes. Moreover, we extend the strategy to the non-maximally entangled EPR channels. In the end, we discuss the potential strategy to improve our scheme including eliminating the encoding step for the error correction codes. Even through the operational errors may occur at the repeater nodes, the performance analysis demonstrates that the scheme significantly preserves the valuable entangled resources and reduces the operational complexity, illustrating the robustness to against the operational errors in repeater nodes.

A High-Precision Flat-Top Pulsed Power Supply Topology Based on SFPFN and Active Coupled Inductor Filter

This study presents a power supply topology capable of generating a large current pulse with a long flat-top duration and a high output voltage. The proposed topology is based on the sequentially fired pulse forming network (SFPFN) and the active coupled inductor filter. The SFPFN generates the primary inaccurate current pulse, and the filter then shapes the current to achieve accurate output. In order to achieve the required accuracy, a novel active coupled inductor filter is proposed which consists of a switched-mode compensator, an auxiliary thyristor pair, a DC bias capacitor, and a coupled inductor. It is designed to deviate most of the voltage and current stress to the coupled inductor, the auxiliary thyristor pair, and the DC bias capacitor, thus reducing the semiconductor devices requirements of the switched-mode compensator. Experimental results based on a 335 A low-power prototype verified the capability of the proposed topology to produce high-precision current pulses and the potential to be generalized to high-power scenarios.

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at Vid = 1 mV and VCM = 0.7 V with VDD = 1.2 V and fs = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ.

Research of Continuous Delta-Sigma Analog-to-Digital Converter for Bio-Electricity Signal Acquisition

In this paper, a continuous delta-sigma analog-to-digital converter with a low power, single-ring, third-order mixed integrator for bio-electricity signal acquisition is proposed. For the trade-off between low power consumption and high resolution, the Active-RC integrator is used in the first-order of the third-order feedforward modulator and the Gm-C integrator with improved linearity is adopted for the second and third order integrators. Because of the infinite resistance provided by the Gm-C integrator, the first-order integrator can replace the traditional second-order operational transconductance amplifier (OTA) with a single-stage OTA operating in the weak invert region to achieve low power consumption and ensure the output swing of the first-order integrator. The structure of cascade-of-integrators with feedforward (CIFF) can scale the output voltage values of three integrators and reduce the requirement of linearity of the Gm-C integrator, to reduce the design difficulty of the Gm-C integrator. In addition, the linearity of the second and third-order Gm-C integrator is improved by using the auxiliary difference pair OTA with source-level negative feedback. Therefore, the matching between the circuit structure and the model coefficients is improved significantly.

Fast Y-Type Thyristor-Based DC SSCB Using Complementary Commutation in a Capacitor–Capacitor Pair Structure

This article proposes a new thyristor-based dc solid-state circuit breaker (SSCB) named Y-type. Main contributions focus on a new complementary commutation circuit including a capacitor–capacitor pair, which features three remarkable advantages. First, a fast commutation is achieved using a countercurrent pulse injection by the capacitor–capacitor pair structure. Second, metal-oxide varistors (MOVs) are disconnected from the power line when SSCB is <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> , which solves the reliability issue due to the MOV degradation and enhances the voltage utilization rate of the main switch. Third, benefiting from the capacitor–capacitor pair structure, reliable reclosing and rebreaking are obtained for practical applications. Experiments are conducted on a 400 V/120 A prototype to validate the proposed Y-SSCB. The peak voltage on the main and auxiliary thyristors reaches 773 and 400 V, respectively. Also, the peak voltage on the auxiliary capacitors pair reaches 740 and 400 V. The Y-SSCB achieves a fast reaction time of 80 μs in interrupting 120 A short-circuit fault current.

Analysis of strong-arm comparator with auxiliary pair for offset calibration

This paper analyzes the principle of the input-referred off calibration using the auxiliary pair for Strong-Arm comparator as well as its impact from the additional common-mode current and parasitic capacitance on the input-referred noise, offset, and decision time in detail. The comparison with the simulation results demonstrates the accurate prediction with the proposed analysis. This paper also discusses the design guideline to optimize the Strong-Arm comparator with the auxiliary pair for offset calibration.

Edge counts for the auxiliary pair graph within the graphical unitary group approach

Closed-form expressions are presented for the numbers of edges in the auxiliary pair graphs (APGs) associated with non spin–orbit and spin–orbit Shavitt graphs for full configuration interaction expansions. A Shavitt graph is a visual representation of a configuration state function expansion space constructed via the graphical unitary group approach (GUGA). An APG is an organisational aid and a programmatic tool generated from a Shavitt graph. The number of edges in an APG determines bounds on the computational scaling as a function of the total numbers of electrons, orbitals, and spin multiplicities. The edge counts extend a suite of Shavitt graph statistics based on these functional parameters. The derivation and the presentation of the formulas for the edge counts has been assisted by the bra–ket interchange symmetry and the particle-hole interchange symmetry in the GUGA formalism. These symmetry operators produce one-to-one correspondences between various sets of edges, and this yields identities among some edge count formulas. There are 208 possible edge types. Of these, some do not contribute to two-electron operators, some are related by bra–ket interchange symmetry, and some are related by particle-hole interchange symmetry. For the remaining unique edge types, explicit expressions are derived for the numbers of edges.

Gating and modulation of a hetero-octameric AMPA glutamate receptor.

AMPA receptors (AMPARs) mediate the majority of excitatory transmission in the brain and enable the synaptic plasticity that underlies learning1. A diverse array of AMPAR signalling complexes are established by receptor auxiliary subunits, which associate with the AMPAR in various combinations to modulate trafficking, gating and synaptic strength2. However, their mechanisms of action are poorly understood. Here we determine cryo-electron microscopy structures of the heteromeric GluA1-GluA2 receptor assembled with both TARP-γ8 and CNIH2, the predominant AMPAR complex in the forebrain, in both resting and active states. Two TARP-γ8 and two CNIH2 subunits insert at distinct sites beneath the ligand-binding domains of the receptor, with site-specific lipids shaping each interaction and affecting the gating regulation of the AMPARs. Activation of the receptor leads to asymmetry between GluA1 and GluA2 along the ion conduction path and an outward expansion of the channel triggers counter-rotations of both auxiliary subunit pairs, promoting the active-state conformation. In addition, both TARP-γ8 and CNIH2 pivot towards the pore exit upon activation, extending their reach for cytoplasmic receptor elements. CNIH2 achieves this through its uniquely extended M2 helix, which has transformed this endoplasmic reticulum-export factor into a powerful AMPAR modulator that is capable of providing hippocampal pyramidal neurons with their integrative synaptic properties.

A novel noble-metal-free binary and ternary In2S3 photocatalyst with WC and “W-Mo auxiliary pairs” for highly-efficient visible-light hydrogen evolution

Herein, noble-metal-free In2S3-WC and In2S3-based photocatalysts with dual cocatalysts of flower-like MoS2 and bulk WC were synthesized through a facile solvothermal reaction. Electrochemical results indicated WC increased the interface conductance of photocatalyst and boosted the transference of photogenerated carriers. The optimal In2S3-WC show a hydrogen production rate of 128.11 μmol·h−1·g−1, which is around 6 times higher than In2S3-1%Pt (20.73 μmol·h−1·g−1). The above results demonstrate commercial WC has a crucial impact of replacing precious metal and separating carriers. Morphology characterization exhibited hydrangea In2S3 and flower-like MoS2 were attached to bulk WC. Gratifyingly, photocurrent, impedance and photoluminescence results demonstrated MoS2 further effectively separated the photogenerated carriers. Remarkably, the higher hydrogen generation rate of 390.52 μmol·h−1·g−1 obtained by the optimal ternary In2S3-WC-MoS2 composite was around 3 and 18 times higher than the optimal In2S3-WC and In2S3-1% Pt. The photocatalytic results demonstrated that "W-Mo auxiliary pairs" was a great efficient synergistic cocatalyst for In2S3 to increase active sites and improve e--h+ pairs separation for H2 generation. Furthermore, a probable reaction mechanism of the enhanced photocatalytic H2 generation was also proposed. This presented research provides an effective concept to design novel and efficient noble-metal-free photocatalyst with "W-Mo auxiliary pairs" for prominent H2 generation activity.

Design of low power single-stage bias current control technique- based DVGA for LTE receivers

In this study, a novel single-stage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The proposed DVGA combines two transimpedance amplifiers, a transconductance amplifier and a novel digitally controlled current. Using a digital control block, an auxiliary pair to retain a constant current density enabled changing the gain. The Heuristic Method was used to optimize the proposed circuit performance for a high gain, low noise and low power consumption. This circuit was simulated using device-level description of TSMC 0.18 µm CMOS process. The VGA achieved 59 dB gain control range, 171 MHz bandwidth, 11.5 dBm third-order input-intercept point as a minimum gain and below 19 dB noise figure as a maximum gain which makes it convenient for LTE receivers. For maximum gain, The Total Harmonic Distortion (THD) is less than -62 dB. The fully differential VGA has a low THD which it represents a key performance satisfying the LTE system application requirements. The overall power consumption of the circuit is 0.35 mW for ± 0.9 V power supply. This paper also dealt with the prediction of optimized DVGA performances for the upcoming CMOS nanoprocess using the robust Bisquare Weights (BW) method for 16 to 10 nm process nodes. The behavior of the optimized DVGA performances with process scaling was detailed.

Friction Characteristics of Surface Nitriding Modification Layer of Ti-6Al-4V ELI Titanium Alloy in Seawater Environment

In order to study the tribological properties of titanium alloy materials and reinforced PTFE pairs treated by surface nitriding modification in seawater environment under low speed and high load, the physical properties of surface nitriding modified treatment were observed and measured with Ti-6Al-4V ELI as the substrate, and the samples of substrate and surface nitriding were modified as disks to 25% fiberglass , 15% glass fiber +5% graphite and 60% tin bronze reinforced PTFE as distribution pins, the friction properties of substrate and surface nitriding modification layer in seawater environment were studied by friction tester. The results show that the friction coefficient between titanium alloy and auxiliary pair is above 0.1, the friction coefficient of titanium alloy surface treatment specimen is lower than that of TC4 titanium alloy, the wear of surface nitriding modified treatment sample is significantly slight, the friction coefficient of 60% tin bronze distribution is the highest, and the friction coefficient of 15% fiberglass +5% graphite is about 15% higher.

Membrane-Free Redox Electrochemical Cell Towards Large Scale Energy Storage

Renewable energy sources are forecasted to supply half of the global energy demand in the future. Development of improved and cost-effective energy storage methods are in high demand due to the intermittency and locally distributed nature of renewable energy sources [1]. Redox flow battery (RFB) is a candidate technology for large-scale energy storage that can be coupled with renewable energy to alleviate intermittency problem [2]. A major contributor to the cost (40%) of RFB is the polymer electrolyte membrane, which is supposed to separate the catholyte and the anolyte [3]. Here, we propose membrane-free design wherein the classical anolyte and catholyte compartment, each with a redox auxiliary electrode pair, are connected by a metal wire. This design relieves the restriction of finding a common electrolyte for the anode and cathode chamber and eliminates the cross-over of undesirable ions between the two chambers. Thus, the new design offers the flexibility of using a wide variety of redox electrolytes (alkaline/acidic or aqueous/non-aqueous) in anode and cathode chambers independently [4]. For example, two compartment redox cell with a pair of auxiliary electrode allows the use of aqueous (acidic/alkaline) or nonaqueous (acidic/alkaline) electrolytes in anode and cathode chambers independent of one another, with electron conducting material connecting the auxiliary electrodes in both chambers during charging and discharging reactions as shown in Figure 1. When oxidation occurs at the anode, corresponding auxiliary electrode udergoes reduction and hence an oxidized materials must be supplied here. Whereas, reduction occurs at the cathode and corresponding auxiliary electrode udergoes oxidation and hence a reduced materials must be supplied to enable a spontaenous charging and discharging of the redox electrolyte. The novel design helps couple spatially separated oxidation and reduction processes. Since, there is no membrane and mass transport across the chambers, the cost, performance, and degradation issues related to membrane are avoided. Alkaline and acidic electrolytes can be used indepenedent of the content in the other chamber. When the solubility of one type of redox electrolyte is limited or zero in aqueous solvent, that particular redox electrolyte alone can be dissolved in a different media/solvent and retain the counter electrolyte in aqueous based solvent [5]. Acknowledgements This research was undertaken thanks in part to funding from the University of Calgary and the Canada First Research Excellence Fund.

A wide linear range CMOS OTA and its application in continuous-time filters

In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency continuous time filters. A second-order fully differential filter architecture is also implemented by using this proposed OTA. The linear OTA and the filter are implemented in SCL 180 nm CMOS process technology with 1.8 V supply voltage. The proposed OTA achieves third order harmonic distortion ($${\textit{HD}}_3$$) of $$-\,74.3$$ dB, inter modulation distortion ($${\textit{IM}}_3$$) of $$-\,75.5$$ dB for $$600\,\hbox{mV}_{p-p}$$ differential input with 1 MHz signal frequency and a linear range of 0.9 V for 1% transconductance variation. The filter is designed for 100 kHz cutoff frequency and achieves $${\textit{HD}}_3$$ of $$-\,68.75$$ dB and $${\textit{IM}}_3$$ of $$-\,64.3$$ dB for $$300\,\hbox{mV}_{p-p}$$, 10 kHz input signal.

Formal Higher Spin Gravities

We present a complete solution to the problem of Formal Higher Spin Gravities — formally consistent field equations that gauge a given higher spin algebra and describe free higher spin fields upon linearization. The problem is shown to be equivalent to constructing a certain deformation of the higher spin algebra as an associative algebra. Given this deformation, all interaction vertices are explicitly constructed. All formal solutions of the equations are explicitly described in terms of an auxiliary Lax pair, the deformation parameter playing the role of the spectral one. We also discuss a natural set of observables associated to such theories, including the holographic correlation functions. As an application, we give another form of the Type-B formal Higher Spin Gravity and discuss a number of systems in five dimensions.

Time-dependent pair density functional theory

Time-dependent pair density functional theory is presented. The Runge-Gross theorem is extended to the pair density and proved. A “non-interacting scheme” of electron pairs is constructed via adiabatic connection. Equations for the auxiliary pair functions are derived.

A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54[Formula: see text]dB (from 54[Formula: see text]dB to 0[Formula: see text]dB) with a 3[Formula: see text]dB BW over more than 110[Formula: see text]MHz. The circuit consumes the maximum power of 0.65[Formula: see text]mW from a 1.8[Formula: see text]V supply.

Latent homomorphism and content satisfaction: The double life of Turkic auxiliary &lt;i&gt;–(İ)p bol–&lt;/i&gt;

This paper argues that the Turkic auxiliary construction –(İ)p bol–, at least in Uyghur and Uzbek, is actually a pair of auxiliaries with distinct meanings. The first auxiliary is described as expressing “full completion” of the event, but its use is highly restricted, to events with incremental or universally quantified themes. Using targeted context-based elicitation, we find that the expression of completion is indirect. Instead, the auxiliary asserts that the event description is homomorphic, in that all of its events are both event-mapped and theme-mapped. Homomorphism requires every part of the theme to undergo a part of the event, and this derives the reported sense of completion.The second auxiliary is not attested in the literature. It applies to all kinds of events, and expresses what we call “content satisfaction,” the conventional implicature that the event as described satisfies some salient propositional content by rendering it true. For instance, it makes part of a plan come to fruition. This plan is presupposed, and the content is accessible through a content-generating function.We apply the methodologies of formal semantic fieldwork to tease these auxiliaries apart, including scope tests that apply differently to the two auxiliaries. Having distinguished them, we suggest new ways to typologically distinguish Turkic auxiliaries and auxiliaries cross-linguistically.

Numerical Solution to the Dirichlet Control Problem on a Part of the Boundary for the Petrovsky system

Abstract For the Euler-Bernoulli plate equation the Dirichlet control problem is considered. To solve this problem numerically, a combination of classical regularization methods and a scheme of compact embedding of the spaces of optimal regularity into an auxiliary pair of spaces is used. Estimates of the uniform proximity of the exact and approximate operators in the new pair of spaces are obtained.