Automatic Test Pattern Generation Research Articles

Software-Based Self-Testing of Embedded Processors

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

Optimized reseeding by seed ordering and encoding

Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of seeds determines the required storage either on the ATE or the chip being tested. These techniques interleave pseudorandom and deterministic cycles rather than first applying all of the pseudorandom cycles and then the deterministic cycles. The decision of when to change from a pseudorandom cycle to a deterministic cycle is made by comparing the final state of the pseudorandom cycle with previously generated ATPG patterns or by carrying out fault simulation on the final state. Which deterministic pattern is chosen for the deterministic cycle critically influences the remainder of the test. A methodology for doing this is described. In addition to interleaving test cycles, it is possible to use partial cycles in which the PRPG operates for a few clocks without loading the scan chains. This allows a new seed to be present without loading the seed from the ATE or controller. As might be suspected, this reduces the number of stored seeds at the penalty of more complexity in the control sequence. These techniques were simulated and compared with conventional reseeding for some ISCAS'89 benchmarks. Improvements varied between 25% and 85% in the required seed storage.

Optimal Interconnect ATPG Under a Ground-Bounce Constraint

In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time.

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.

Advances in VLSI testing at MultiGb per second rates

Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability) methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment) resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator) patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

Logic-level mapping of high-level faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phas...

Modeling Custom Digital Circuits for Test

Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuck-faults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15--20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.

Overcoming Fault Test Coverage with Time-Resolved Emission (TRE) Probing

We discuss an approach to combining internal logic waveform measurements with automated test pattern generation (ATPG) tools. The internal logic waveform measurements, provided by time-resolved emission (TRE) technology, localized the root-caused of a failure that was ambiguous from the ATPG analysis alone.

Automatic circuit extractor for HDL description using program slicing

Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.

Logic-level mapping of high-level faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available.On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model?The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology.

Fault Testing for Reversible Circuits

Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test-set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test-set constructions for the standard stuck-at fault model, as well as the usually intractable cell-fault model. We also give a practical test-set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation.

Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.

A New ATPG Technique (MultiDetect) for Testing of Analog Macros in Mixed-Signal Circuits

A new test-set selection technique based on the frequency-domain testing of analog circuits is presented in this paper. We propose a new automatic test pattern generation (ATPG) method known as MultiDetect for testing linear time invariant (LTI) circuits. The proposed technique is best suited for use of existing building blocks in systems-on-chip for implementation of an on-chip test-signal generator and test-response analyzer. The generated test set with the MultiDetect method can effectively detect and diagnose both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as built-in self-test (BIST). Testing of analog blocks based on circuit-transfer function makes our ATPG a general purpose method for all kinds of LTI circuits. A new novel test method causing the device under test to saturate or get out of saturation, to detect a fault with simple detection hardware, is also introduced in this paper. In our proposed novel test scheme, usage of a single sinusoid as a test signal when compared to multitone signal, and detection of faults with digital counting technique, facilitate the test implementation with simple BIST hardware and make testing more cost effective. The sinusoid is a very useful waveform for testing and analyzing LTI circuits. In the steady state, both the input and output of a stable LTI circuit are sinusoids of the same frequency. The relationship between the amplitudes and phase angles of the input and output sinusoids is frequency-dependent. Identification of a sinusoid that detects more faults results in an optimized test signal set. The technique used in the MultiDetect method for identification of a sinusoid results in an efficient compacted test set. The search for fault diagnosis is restricted to a limited set of faults, making diagnosis fast in the MultiDetect method. A methodology for test-set compaction of the MultiDetect technique is described and results of experiments on various test circuits are discussed. The proposed method is seen to be efficient for low-power applications. The experimental results show that the testing of LTI circuits using the MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time.

XID: Don't Care Identification of Test Patterns for Combinational Circuits

Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit, some of the primary input values may be changed to the opposite logic values without losing fault coverage. We can regard such input values as don't care (X). In this paper, we propose a method for identifying the X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including as many X inputs as possible, by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms. Experimental results for ISCAS benchmark circuits show that approximately 69% of the inputs of uncompacted test sets could be X on the average. Even for highly compacted test sets, the method found that approximately 48% of inputs are X.

A simplifier for propositional formulas with many binary clauses.

Deciding whether a propositional formula in conjunctive normal form is satisfiable (SAT) is an NP-complete problem. The problem becomes linear when the formula contains binary clauses only. Interestingly, the reduction to SAT of a number of well-known and important problems--such as classical AI planning and automatic test pattern generation for circuits--yields formulas containing many binary clauses. In this paper we introduce and experiment with 2-SIMPLIFY, a formula simplifier targeted at such problems. 2-SIMPLIFY constructs the transitive closure of the implication graph corresponding to the binary clauses in the formula and uses this graph to deduce new unit literals. The deduced literals are used to simplify the formula and update the graph, and so on, until stabilization. Finally, we use the graph to construct an equivalent, simpler set of binary clauses. Experimental evaluation of this simplifier on a number of bench-mark formulas produced by encoding AI planning problems prove 2-SIMPLIFY to be a useful tool in many circumstances.

ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems

Globally Asynchronous, Locally Synchronous (GALS) systems are now commonplace in many cost-critical and life-critical applications, thus motivating the need for a systematic approach to verify functionality. The complexity of the verification problem for large heterogeneous GALS systems necessitates the development of simulation-based validation approaches to uniformly validate hardware, software, and their interaction. GALS systems are comprised of several processes which may be mapped to different hardware and software components and communicate through asynchronous interfaces. Communication between these processes must be verified to ensure that the system is working correctly. Previous work focuses on checking the correctness of individual processes rather than communication between multiple processes. Timing errors may cause a signal to have an incorrect value for a short time period. Timing errors can cause a problem in GALS systems if the value of a signal with a timing error is used while is has an incorrect value. This paper presents an automatic test pattern generation (ATPG) tool to generate tests for timing-induced functional errors.

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits

High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with porch steps and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-/spl mu/m process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.

A novel RTL behavioral description based ATPG method

The paper proposes a novel ATPG (Automatic Test Pattern Generation) method based on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware Description Language). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptions to Process Controlling Trees (PCT)and Data Dependency Graphs (DDG), which are used for behavioral simulation and data tracing. Transfer faults are extracted from DDG edges, which compose a fault set needed for test generation. Then, simulation begins without specifying inputs in advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally, when the simulation ends, the partially fixed input sequence is the generated test sequence. The proposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to cover uncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests with good quality. Experimental results demonstrate that the proposed method is better than ARTIST in three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length is shorter by 52%; and (3) the fault coverage is higher by 0.89%.

APPLYING QUANTUM SEARCH TO AUTOMATED TEST PATTERN GENERATION FOR VLSI CIRCUITS

This paper presents a quantum search algorithm for Automated Test Pattern Generation (ATPG) of VLSI circuits. For given digital circuits, a neural network is created that represents the digital gates with their interconnections as neurons. This neural network is characterized by an energy function E, which is the mathematics representation of neural network. The solution of the energy function gives us the test vector. The test vector is a combination of input values of digital circuits that detects a particular fault. In this paper, specific aspects of quantum theory like superposition and quantum parallelism are applied to find the solution of this energy function. The algorithm developed is so efficient that it requires only [Formula: see text] (where N is the total number of vectors) iterations to find the desired test vector whereas in classical computing, it takes N/2 iterations. At the end, a comparison is made between exhaustive, simulated annealing and quantum based techniques. Experimental results show that the quantum search algorithms are more efficient than classical algorithms and can be applied with more efficiency.

Behavioral test generation/fault simulation

A complete behavioral fault simulation and automatic test pattern generation (ATPG) system for circuits modeled in VHDL has been presented in this research. Ten different behavioral fault models were selected and used to generate test patterns through fault simulation. One major advantage of the current system is that full VHDL (IEEE-STD 1076) constructs can be handled because fault simulation are performed by comparing the simulation results of good and faulty models utilizing a VHDL simulator. Areas of future research include the refinement of existing fault models, defining new behavioral fault models to reduce the gap between the behavioral fault models and gate-level failures, and the development of a better test pattern generator for target faults. Another valuable enhancement would be to run fault simulation in parallel, by embedding multiple faulty models into one test bench to simulate many faults concurrently. This would speed up the behavioral fault simulation in an efficient way. Gate-level fault simulation is not an effective solution for complex microcircuits. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC).