Automatic Synthesis Algorithm Research Articles

Calculation automation of “cemented doublet with a singlet” and “singlet with a cemented doublet” objectives

Subject of study. Automating the synthesis of “cemented doublet with a singlet” and “singlet with a cemented doublet” objectives with an entrance pupil on the first surface of the system is studied. The design of this type of system is complex owing to a large number of possible solutions. Moreover, when changing over from an infinitely thin system to a system with a finite thickness of elements, the image quality of axial points significantly deteriorates in most cases. This feature should be considered when developing an algorithm for lens design. Aim of study. The aim is to develop a method and algorithm for automatic synthesis of “cemented doublet with a singlet” and “singlet with a cemented doublet” objectives and a ranking system for designed objectives. Changes in the axial point image quality of the considered objectives with two or three different materials for possible acceleration of the synthesis process are also studied. Method. The initial design of objectives is carried out on the basis of the third-order aberrations theory. An automated exhaustive search is used to rank all possible combinations of lens materials. Main results. The methodology and algorithm of the automatic design of “cemented doublet with a singlet” and “singlet with a cemented doublet” objectives have been developed. A ranking system is provided to rank the designed objectives by the main criterion based on the axial point image size and by the preliminary criterion that determines the technological stability of the objective to the manufacturing errors of the optical elements. It is determined that the “singlet with a cemented doublet” objectives are generally preferable to “cemented doublet with a singlet” objectives according to the proposed criteria. Based on the calculation results, it is demonstrated that solutions with only two materials can have a slight decrease in the image quality of the axial point. Practical significance. Based on the developed algorithm, the program for the automatic design of two- and three-lens objectives is upgraded. The developed program will help optical engineers to significantly simplify and accelerate the process involved in designing two- and three-lens objectives with the required image quality characteristics.

Multiobject Design of a 3-D-Printed All-Dielectric Lens Antenna by an Automatic Synthesis Algorithm

Multiperformance indices of an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> -band three-dimensional (3-D)-printed all-dielectric lens antenna are fulfilled by an automatic synthesis algorithm. By hybridizing particle swarm optimization and genetic algorithm optimization, the algorithm possesses the advantages of fast optimization and avoiding of local optimum. Multiobjective subfunctions are defined to realize multiperformance indices, and the objective subfunctions are customized to make the optimization process more efficient. As the all-dielectric lens is optimized, the source horn is included to direct acquire the performance indices (| <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> |, axial ratio, and gain), which makes the optimization process efficient and accurate. Moreover, the optimization process is automatic as the structure modeling and sizing are performed automatically. The proposed lens antenna has good <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> , axial ratio, and gain performances in the 60–90 GHz band, which shows that the algorithm is a powerful method for multiple goals.

A non-navigational TIN-DDM automatic synthesis algorithm that takes into account the accurate determination of terrain features and full expression of topography

A non-navigational TIN-DDM automatic synthesis algorithm that takes into account the accurate determination of terrain features and full expression of topography

Automatic synthesis of compliant forceps for robot-assisted minimally invasive surgery

Abstract Due to its monolithic structure and high dexterity, the compliant mechanism becomes an emerging solution to miniaturize surgical forceps for minimally invasive procedures. However, it is complicated and inefficient to use traditional rigid-link-based kinematic method to synthesize compliant forceps. In this paper, we present a topology-optimization-based method to automatically synthesize compliant forceps for robot-assisted minimally invasive surgery (RMIS). The basic geometry modeling tool and the automatic synthesis algorithm were both implemented in Matlab. Several synthesis examples were presented to show the performance of the proposed method. The realized forceps and a continuum manipulator have been constructed and 3D-printed, which demonstrated the application of the automatic synthesis method in RMIS.

A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

Using Event Logs for Local Correction of Process Models

During the life-cycle of an Information System (IS) its actual behavior may not correspond to the original system model. However, to the IS support it is very important to have the latest model that reflects the current system behavior. To correct the model the information from the event log of the system may be used. In this paper, we consider the problem of process model adjustment (correction) using the information from event log. The input data for this task is the initial process model (a Petri net) and an event log. The result of correction should be a new process model, better reflecting the real IS behavior than the initial model. The new model could be also built from scratch, for example, with the help of one of the known algorithms for automatic synthesis of the process model from an event log. However, this may lead to crucial changes in the structure of the original model, and it will be difficult to compare the new model with the initial one, hindering its understanding and analysis. Then it is important to keep the initial structure of the model as much as possible. In this paper we propose a method for process model correction based on the principle of “divide and conquer”. The initial model is decomposed into several fragments. For each of the fragments its conformance to the event log is checked. Fragments, which do not match the log, are replaced by newly synthesized ones. The new model is then assembled from the fragments via transition fusion. The experiments demonstrate that our correction algorithm gives good results when it is used for correcting local discrepancies. The paper presents the description of the algorithm, the formal justification for its correctness, as well as the results of experimental testing on artificial examples.

A Message Passing Algorithm for Automatic Synthesis of Probabilistic Fault Detectors from Building Automation Ontologies

Model-based fault diagnosis has been indicated as a fundamental method in enabling optimal maintenance of buildings, thus leading to important energy savings. However, accurate models of buildings and their technical equipment are seldom available, and this lack of knowledge applies even more to descriptions of modeling and measurement uncertainties, which are needed for developing robust fault detection thresholds with given performances in terms of False Alarm Rates. In the present paper we propose to overcome both limitations, by introducing: 1) a methodology for the automatic synthesis of a global model of a building and its equipment, leveraging a purposely built ontology-based Building Information Model; and 2) a novel message passing algorithm called MP-BUP for automatically propagating the effects of uncertainties in interconnected bilinear systems and derive robust probabilistic thresholds.

Using Event Logs for Local Correction of Process Models

During the life-cycle of an Information System (IS) its actual behaviour may not correspond to the original system model. However, to the IS support it is very important to have the latest model that reflects the current system behaviour. To correct the model, the information from the event log of the system may be used. In this paper, we consider the problem of process model adjustment (correction) using the information from an event log. The input data for this task are the initial process model (a Petri net) and the event log. The result of correction should be a new process model, better reflecting the real IS behavior than the initial model. The new model could be also built from scratch, for example, with the help of one of the known algorithms for automatic synthesis of the process model from an event log. However, this may lead to crucial changes in the structure of the original model, and it will be difficult to compare the new model with the initial one, hindering its understanding and analysis. It is important to keep the initial structure of the model as much as possible. In this paper, we propose a method for process model correction based on the principle of “divide and conquer”. The initial model is decomposed in several fragments. For each fragment its conformance to the event log is checked. Fragments which do not match the log are replaced by newly synthesized ones. The new model is then assembled from the fragments via transition fusion. The experiments demonstrate that our correction algorithm gives good results when it is used for correcting local discrepancies. The paper presents the description of the algorithm, the formal justification for its correctness, as well as the results of experimental testing by some artificial examples.

Compositionality in synchronous data flow

Hierarchical SDF models are not compositional: a composite SDF actor cannot be represented as an atomic SDF actor without loss of information that can lead to rate inconsistency or deadlock. Motivated by the need for incremental and modular code generation from hierarchical SDF models, we introduce in this paper DSSF profiles. DSSF (Deterministic SDF with Shared FIFOs) forms a compositional abstraction of composite actors that can be used for modular compilation. We provide algorithms for automatic synthesis of non-monolithic DSSF profiles of composite actors given DSSF profiles of their sub-actors. We show how different trade-offs can be explored when synthesizing such profiles, in terms of compactness (keeping the size of the generated DSSF profile small) versus reusability (maintaining necessary information to preserve rate consistency and deadlock-absence) as well as algorithmic complexity. We show that our method guarantees maximal reusability and report on a prototype implementation.

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays

Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automatic synthesis algorithm for the architecture. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks.

AniPaint: Interactive Painterly Animation from Video

This paper presents an interactive system for creating painterly animation from video sequences. Previous approaches to painterly animation typically emphasize either purely automatic stroke synthesis or purely manual stroke key framing. Our system supports a spectrum of interaction between these two approaches which allows the user more direct control over stroke synthesis. We introduce an approach for controlling the results of painterly animation: keyframed Control Strokes can affect automatic stroke's placement, orientation, movement, and color. Furthermore, we introduce a new automatic synthesis algorithm that traces strokes through a video sequence in a greedy manner, but, instead of a vector field, uses an objective function to guide placement. This allows the method to capture fine details, respect region boundaries, and achieve greater temporal coherence than previous methods. All editing is performed with a WYSIWYG interface where the user can directly refine the animation. We demonstrate a variety of examples using both automatic and user-guided results, with a variety of styles and source videos.

Scenario-Based Specification of Automotive Requirements With Quantitative Constraints and Synthesis of SL/SF Monitors

Requirements of embedded systems often describe the system behavior with quantitative constraints over parameters such as timing, memory, and other resources. In this letter, we present a visual language suited for scenario-based specification of requirements with quantitative constraints. Our language, known as event sequence charts with quantitative constraints (ESC-QC), is inspired by message sequence charts (MSC) and its variants. We introduce ESC-QC notations through an example from automotive requirements and then describe the formal syntax and semantics. Besides being useful for formal documentation and analysis of system requirements, ESC-QC specifications can be translated into monitors and used for run-time verification of designs. In automotive systems Simulink/Stateflow (SL/SF) is widely used for design of control systems. We have developed an algorithm for automatic synthesis of SL/SF monitors from ESC-QC specifications. We have used this algorithm for generating monitors for verification of controller models from active safety and body control applications.

An algorithm for synthesis of large time-constrained heterogeneous adaptive systems

Large time-constrained applications are highly computer-intensive and are often implemented as a complex organization of pipelined data parallel tasks on a pool of embedded processors, DSP processors, and FPGAs. The large number of design alternatives available at each task level, the application as a whole, and the special needs of the reconfigurable devices (such as the FPGA) make the manual synthesis of such systems very tedious. The automatic synthesis algorithm in this paper combines exact (MILP-based) and heuristic techniques to solve this problem, which basically involves (1) propagation of timing constraints; (2) pipelining the loops to meet throughput requirements; (3) resource selection and scheduling, keeping the processing requirements and the timing constraints in view; (4) scheduling the resources across the tasks to ensure maximum utilization; and (5) hiding the reconfiguration delays of the FPGAs. While the use of MILP techniques helps in getting high-quality results, combining them with heuristics ensures acceptable synthesis times, striking a good balance between quality of results and synthesis time. Our experimental evaluation of the algorithm shows an average 40% in resource cost reduction (compared to manual synthesis) with synthesis times from minutes to as low as a few seconds in some cases.

On the Use of Symbolic Analyzers in Circuit Synthesis

In this paper several examples of circuits obtained with an automatic synthesis algorithm will be shown. The algorithm, described in a companion paper [1] and outlined here for clarity, has been implemented in the Mathematica^™ language. We applied the new algorithm to classical problems of inmittance synthesis, obtaining well known topologies and also non-reported structures. When the algorithm is applied to challenging new problems, novel and practically useful inmittances are synthesized.

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits

This paper describes a new scheduling algorithm for automatic synthesis of the control blocks of control-dominated circuits. The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.

A new approach to schedule operations across nested-ifs and nested-loops

This paper presents a new global scheduling algorithm for automatic synthesis of the control blocks of special-purpose microprocessors. The main distinction of the proposed algorithm is that it exploits the inheritances of structured programs. The optimization goal is to maximize the speedup of the processor and minimize the size of the control block. If compared with existing global scheduling algorithms such as Trace scheduling, Tree compaction, and Percolation scheduling, the proposed algorithm consistently achieves better results in terms of the speedup of the processor and the size of the control block.

Computerized optimum design and dynamic simulation of heat exchanger networks

To assist the design engineer to more flexible and controllable, near optimum cost, heat exchanger networks, a computer program, called CAD-HEN (Computer Aided Design of Heat Exchanger Networks), based on thermodynamic principles, was developed. Dynamic simulation and response analysis of the heat exchanger network can be done by the SpeedUp dynamic process simulator by using a specific model. CAD-HEN handles supertargeting, synthesis, and optimization of a heat exchanger network. The targeting and optimization procedures are graphical and interactive. The user views various plots, such as Total Cost Target profile and Grand Composite Curves. An automatic synthesis algorithm, based on the vertical heat transfer model is used to generate in the stream grid environment a near minimum surface network which is optimized with a simplified loop breaking algorithm. A specific model for SpeedUp was developed in order to proceed at dynamic simulation and detailed control study of an existing heat exchanger network.