Automatic Test Program Generation Research Articles

Is This a System?

There are many areas of design and test for which we have widely known solutions, often involving published algorithms and standards. Take Automatic Test Program Generation (ATPG), for instance. You can read about ATPG algorithms in textbooks, the literature is widely available, and most IC test engineers use commercially available ATPG tools.

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Very long instruction word (VLIW) processors are increasingly employed in a large range of embedded signal processing applications, mainly due to their ability to provide high performances with reduced clock rate and power consumption. At the same time, there is an increasing request for efficient and optimal test techniques able to detect permanent faults in VLIW processors. Software-based self-test (SBST) methods are a consolidated and effective solution to detect faults in a processor both at the end of the production phase or during the operational life; however, when traditional SBST techniques are applied to VLIW processors, they may prove to be ineffective (especially in terms of size and duration), due to their inability to exploit the parallelism intrinsic in these architectures. In this paper, we present a new method for the automatic generation of efficient test programs specifically oriented to VLIW processors. The method starts from existing test programs based on generic SBST algorithms and automatically generates effective test programs able to reach the same fault coverage, while minimizing the test duration and the test code size. The method consists of four parametric phases and can deal with different VLIW processor models. The main goal of the paper is to show that in the case of VLIW processors, it is possible to automatically generate an effective test program able to achieve high fault coverage with minimal test time and required resources. Experimental data gathered on a case study demonstrate the effectiveness of the proposed approach; results show that this method is able to exploit the intrinsic parallelism of the VLIW processor, taming the growth in size, and duration of the test program when the processor size grows.

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

In this paper, we present a satisfiability (SAT)-based framework for automatically generating test programs that target gate-level stuck-at faults in microprocessors. The microarchitectural description of a processor is first translated into a unified register-transfer level (RTL) circuit description, called assignment decision diagram (ADD), for test analysis. Test generation involves extraction of justification/propagation paths in the unified circuit representation from an embedded module's input-output (I/O) ports to primary I/O ports, abstraction of RTL modules in the justification/propagation paths, and translation of these paths into Boolean clauses in conjunctive normal form (CNF). Additional clauses are added that capture precomputed test vectors/responses at the embedded module's I/O ports. An SAT solver is then invoked to find valid paths that justify the precomputed vectors to primary input ports and propagate the good/faulty responses to primary output ports. Since the ADD is derived directly from a microarchitectural description, the generated test sequences correspond to a test program. If a given SAT instance is not satisfiable, then Boolean implications (also known as the unsatisfiable segment) that are responsible for unsatisfiability are efficiently and accurately identified. We show that adding design for testability (DFT) elements is equivalent to modifying these clauses such that the unsatisfiable segment becomes satisfiable. Test generation at the RTL also imposes a large number of initial conditions that need to be satisfied for successful detection of targeted stuck-at faults. We demonstrate that application of the Boolean constraint propagation (BCP) engine in SAT solvers propagates these conditions leading to significant pruning of the sequential search space which in turn leads to a reduction in test generation time. Experimental results demonstrate an 11.1X speedup in test generation time for test generation at the RTL over a state-of-the-art gate-level sequential generator called MIX, at comparable fault coverages. An unsatisifiability-based DFT approach at the RTL improves this fault coverage to near 100% and incurs very low area overhead (3.1%). Unlike previous approaches that either generate a test program consisting of random instruction sequences or assume the existence of test program templates, the proposed approach constructs test programs in a deterministic fashion from the microarchitectural description of a processor

Microprocessor Architectural Automatic Test Program Generation

In this paper, a novel specification driven and constraints solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented, and its prototype sytem——MA2TG (microprocessor architectural automatic test program generator) is introduced. It can generate not only random test programs but also a sequence of instructions target to specific constraints. The proposed methodology makes three important contributions. First, it simplifies the microprocessor architecture modeling and eases adoption of architecture modification via Architecture Description Language (ADL) specification. Second, it generates test programs for specific constraints utilizing the power of state-of-art constraints solving techniques. Finally, the size of the test program for microprocessor verification and the verification time are dramatically reduced. MA2TG has been applied on DLX processor and the embedded microprocessor EStar to illustrate the usefulness of the approach.

Code Generation for Functional Validation of Pipelined Microprocessors

Functional validation of pipelined microprocessors is a challenging task, as the behavior of a pipeline is determined by a sequence of instructions and by the interaction between their operands. This paper describes an approach to automatic test-program generation based on an evolutionary algorithm. The proposed methodology is able to tackle complex pipelined designs. Human intervention is limited to the formalized listing of the instruction set, and also internal parameters of the test program generator are auto-adapted. A prototype was built and exploited to generate test programs for the DLX/pII, a pipelined microprocessor. For the purpose of these experiments, test programs were devised trying to maximize the RT-level statement coverage. However, the method can be used to generate test programs on different target metrics. Results show the feasibility and effectiveness of the method.

Automatic test program generation: a case study

Design validation is a critical step in the development of present-day microprocessors, and some authors suggest that up to 60% of the design cost is attributable to this activity. Of the numerous activities performed in different stages of the design flow and at different levels of abstraction, we focus on simulation-based design validation performed at the behavioral register-transfer level. Designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness. Simulation results can also be useful in comparing the HDL model against higher-level references or instruction set simulators. Microprocessor validation has become more difficult since the adoption of pipelined architectures, mainly because you can't evaluate the behavior of a pipelined microprocessor by considering one instruction at a time; a pipeline's behavior depends on a sequence of instructions and all their operands.

A BNF-based automatic test program generator for compatible microprocessor verification

A novel Backus-Naur-form- (BNF-) based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. We use X86 architecture to illustrate our design method. Our method is equally applicable to other processor architectures by redefining BNF production rules. Design issues for an automatic program generator (APG) are first outlined. We have resolved the design issues and implemented the APG by a top-down recursive descent parsing method which was originated from compiler design. Our APG can produce not only random test programs but also a sequence of instructions for a specific module to be tested by specifying a user menu-driven file. In addition, test programs generated by our APG have the features of no infinite loop, not entering illegal states, controllable data dependency, flexible program size, and data cache testable. Our method has been shown to be efficient and feasible for the development of an APG compared with other approaches. We have also developed a coverage tool to integrate with the APG. Experimental evaluation of the generated test programs indicates that our APG, with the guidance of the coverage tool, only needs to generate a small number of test programs to sustain high coverage.

Using a constraint satisfaction formulation and solution techniques for random test program generation

Automatic generation of test programs plays a major role in the verification of modern processors and hardware systems. In this paper, we formulate the generation of test programs as a constraint satisfaction problem and develop techniques for dealing with the challenges we face, most notably: huge variable domains (e.g., magnitude of 264) and the need to randomly generate well distributed samplings of the solution space. We describe several applications of our method, which include specific test generators targeted at various parts of a design or stages of the verification process.

ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits

HDL-A is an analog version of the Hardware Description Language which is suitable for structural and behavioral descriptions and simulations of digital, analog, and mixed-signal circuits and systems. This paper presents an automatic test program generator (ATPRG) for fault diagnosis of analog/mixed-signal integrated circuits. The ATPRG is developed under the Mentor Graphics Design system environment, where the units under test (UUT's) are modeled in HDL-A and simulated by Accusim, and AMPLE (Advanced Multi-Purpose Language) in Mentor Graphics Design system environment is used to define and execute the generation process automatically. To increase the reliability and quality, the generated test programs will be verified and validated. A verification process checks if the test programs are generated correctly and if the generated test programs can effectively locate fault(s). The test programs are validated by emulating the UUT's. The actual test can be run in a fully automatic mode, or interactively.

Design Verification of Complex Microprocessors

As the complexity of microprocessors increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for compatible microprocessor designs. To guarantee perfect compatibility with previous microprocessors, we developed three C models in different abstraction levels, i.e. Polaris, MCV and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implemetation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC) are co-simulated with consistency checking between these two models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model (VPC). To increase the confidence level of verifications, Profiler reports the verification coverage of the test program, which is fed-back to the automatic test program generator (Pandora). The Restartability feature also helps to significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the HK486, an Intel 80486 pin-compatible microprocessor successfully.

Integrated Test Solutions for a System Design Environment

While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware support environment for application-specific systems is described which provides a designer with a set of hardware modules and circuitry, that support these standards and software tools for automatic incorporation of testability hardware, as well as automatic test vector and test program generation.

Load balancing in a hybrid ATPG environment

The problem of balancing the computational load between fault simulation and conventional ATPG (automatic test program generation) is treated. A rule for switching from probabilistic to deterministic test pattern computation is derived. The criterion is based on a model of monitoring of the simulation process and on an online estimation of the fault detection probabilities. Using these probabilities and the operation characteristics of the ATPG program, one can decide whether it is more efficient to continue fault simulation or to proceed with algorithmic test pattern computation. A prototype of the hybrid ATPG system was implemented on an Apollo DN3000. Compared to a conventional ATPG system, better coverage and shorter generation times were obtained. >

Automatic test program generation for analog circuits: The self‐testing approach

Abstract An analog automatic test program generation (ATPG) for both linear and nonlinear circuits is developed. This ATPG is based on a self‐testing algorithm and can translate the simple but readable free‐formated network description to generate the associated diagnosis equation so that the desired fault analysis can be conducted. The user can choose either to input the network description directly or to make the ATPG much more user‐friendly by creating the circuit diagram from a graphical terminal. The ATPG code is subdivided into off‐line and on‐line components while the actual test can be run in either a fully automatic mode or an interactive mode.

A Survey of Switch-Level Algorithms

The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuit to its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set of charge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highly simplified way. Switch-level algorithms have been applied to such tasks as logic and fault simulation, formal hardware verification, timing analysis, and automatic test program generation. They have been implemented on sequential and parallel computers as well as by hardware simulation accelerators.

On the Implementation of an Analog ATPG: The Linear Case

In order to reduce the complexity of the fault diagnosis equations and still retain computational simplicity, a self-testing algorithm has been proposed and implemented on a VMS VAX 11/780 for linear circuits. A prototype implementation of such an algorithm for nonlinear circuits and systems is presented. The proposed analog automatic test program generator (AATPG) for nonlinear circuits and systems is divided into offline and online processes. Unlike the simulation of the pseudocircuits in the linear case, which can be achieved by a matrix/vector multiplication, the circuit simulator SPICE is used to simulate the nonlinear pseudocircuits. The automatic SPICE code generator required for this simulation is presented. The proposed AATPG for nonlinear circuits has been implemented on a VMS VAX 11/780. The actual test can be run in either a fully automatic mode or interactively. >

Optimisation of access points for automatic test program generation and fault location in large analogue circuits and systems: M. A. Sarram, J. Hywel Williams, D. R. Towill and K. C. Verghese Radio Electron. Eng.51 (9), 435 (Sept 1981)

Optimisation of access points for automatic test program generation and fault location in large analogue circuits and systems: M. A. Sarram, J. Hywel Williams, D. R. Towill and K. C. Verghese Radio Electron. Eng.51 (9), 435 (Sept 1981)

Analog Modeling Improves Test Programs

The complexity of integrated circuits has increased to the point that the integrated circuit's (IC) internal circuit components affect the ability of in-circuit testers to accurately measure analog components connected externally to the IC. For analog circuit analyzers, the ability to describe the IC's internal electrical equivalent using standard components, R, L, C, etc., improves the automatic analog test program generator's ability to add guards to offset the internal shunts. This article presents a technique for selecting and describing basic component types and component magnitudes within the IC's internal structure.

Optimization of access points for automatic test program generation and fault location in large analogue circuits and systems: M. A. Sarram, J. Hywel Williams, D. R. Towill and K. C. Varghese. Radio Electronic Eng.51 (9), 435 (September 1981)

Optimization of access points for automatic test program generation and fault location in large analogue circuits and systems: M. A. Sarram, J. Hywel Williams, D. R. Towill and K. C. Varghese. Radio Electronic Eng.51 (9), 435 (September 1981)

Optimization of access points for automatic test program generation and fault location in large analogue circuits and systems

The paper develops a methodology for the automatic test program generation (ATPG) for a large analogue circuit subject to component drifts. An optimization algorithm developed selects the best set of intermediate access points for a.c. and d.c. tests of the circuit.During ATPG, faults are simulated by varying each component over a wide range. Voltages measured at all available nodes are thus used in the pre-processing stage of node selection. An optimization procedure based on the discriminating power of measurements and separability between fault signatures is used to select the best set of frequencies applicable for all nodes in a.c. testing. A preamplifier and control amplifier of 56 components is chosen as Unit Under Test (UUT) to demonstrate the ATPG. The fault isolation scheme used is based on the nearest neighbour rule.The rexlationship between diagnosability and number of test features is shown to follow the customary Pareto type curve. However, four carefully chosen nodes and three carefully chosen test frequencies are shown to give an adequate level of diagnosability. The whole scheme is implemented automatically using a minicomputer interfaced to the UUT.

On the use of procedural models for generation of test programs

An approach based on artificial intelligence concepts is developed for automatic generation of test programs for analog circuits. The programs will, with the help of automatic test equipment (ATE), make appropriate measurements and deduce the location of potential faults in analog circuit boards.