Design Automation Environment Research Articles

Development of an electronic block for temperature alarms

The electrical structural and schematic diagrams of the electronic block for temperature-alarm signaling in the ship premises of surface ships and submarines are developed. Elements of the electronic block are described: microcontroller, power circuit, RS-485 buffer with protection, etc. Estimates of power consumption and reliability of the developed electronic block are given. When developing the device, the «Altium Designer» automatic design environment was used. Keywords temperature alarm, electronic block, electrical circuit, reliability, power consumption

IMPLEMENTATION OF THE COINCIDENCE FREQUENCY METER ON FPGA

Means of measuring various parameters and technical characteristics of radio equipment have always occupied leading positions in science and technology. Without an accurate definition of the relevant values, it is impossible to build modern high-quality radio communication systems, radar, navigation ground and satellite systems. In ultrasound diagnostics, which are used in medicine, the speed of blood flow in vessels is studied by determining the frequency of the reflected signal. At the same time, it is necessary to use high-speed frequency measurement tools in systems with active sensors used in telecommunication networks based on Internet of Things technology. For example, in active radar, using the frequency of the reflected signal, it is possible to calculate not only the coordinates, but also the circular speed of the moving target. Modern research is aimed at improving the metrological and technical indicators of existing measuring devices, in particular at developing new methods for correcting the characteristics of the transformation of the measuring channel, which is their main component. At the same time, most digital frequency meters are built on the method of counting the number of pulses N with an unknown period Tx that arrive at the input of the device during a calibrated time interval. All this leads to an increase in measurement time and requires additional hardware costs for fast processing of measurement results. The coincidence method belongs to vernier methods and is promising for use when measuring the frequency of periodic signals. This paper points out the shortcomings of known methods of measuring the frequency of a periodic signal. On the basis of the well-known method of coincidence, a functional scheme of a 16-bit device for measuring frequency, which is implemented on the basis of a FPGA from Intel (Altera), has been developed. The developed coincidence frequency meter has a dynamic range of 96dB. Representation of time diagrams obtained in the Quartus Prime 18.0 automated design environment and confirming the operability of the developed functional scheme of the 16-bit device for frequency measurement by the coincidence method. An analytical dependence for determining the frequency of a periodic signal during frequency measurement by the coincidence method is presented.

A Methodology to Design Static NCL Libraries

The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

Procedure to Create an Automated Design Environment for Functional Assemblies

AbstractManually exploring the solution space for different variants of a product for a given set of requirements is ineffective regarding product development time and adaptation to dynamic customer requirements. Variant generation coupled to optimization algorithms offers possibilities to search the solution space in an automated way. This paper provides a framework to build a generative parametric design environment for functional assemblies by implementing analysis as well as synthesis methods in computer-aided tools. The procedure is presented using the example of a coffee machine.

A Solution to Design Semi-static Null Convention Logic Cell Libraries

The Null Convention Logic (NCL) based asynchronous circuits have eliminated the disadvantages of the synchronous circuits, including noise, glitches, clock skew, power, and electromagnetic interference. However, using NCL based asynchronous designs was not easy for students and researchers because of the lack of standard NCL cell libraries. This paper proposes a solution to design a semi-static NCL cell library used to synthesize NCL based asynchronous designs. This solution will help researchers save time and effort to approach a new method. In this work, NCL cells are designed based on the Process Design Kit 45nm technology. They are simulated at the different corners with the Ocean script and Electronic Design Automation (EDA) environment to extract the timing models and the power models. These models are used to generate a *.lib file, which is converted to a *.db file by the Design Compiler tool to form a complete library of 27 cells. In addition, we synthesize the NCL based full adders to illustrate the success of the proposed library and compare our synthesis results with the results of the other authors. The comparison results indicate that power and delay are improved significantly.

Электронно-микроскопические исследования распределения пор по диаметрам на сорбционной поверхности ультрафильтрационных мембран УАМ-50, УАМ-100, УПМ-К, УПМ-100

В работе обоснована актуальность заявленной тематики, определено место работы среди дру-гих публикаций в области исследования пористости мембран. На основе литературного обзора изуча-емой области и сформулированной цели проведен выбор исследуемых типов ультрафильтрационных мембран, представлены их основные характеристики (рабочее давление, удельный поток растворителя, коэффициент задерживания, рабочий диапазон рН, максимальная температура). Применена методика электронно-микроскопического исследования распределения пор по диаметрам на поверхности уль-трафильтрационных мембран УАМ-50, УАМ-100, УПМ-К, УПМ-100, включающая в себя фиксацию изображения поверхности мембран с помощью электронного микроскопа, перенос в среду автомати-зированного проектирования AutoCad 2018, визуальный выбор четырех равномерных зон, площадью по 1∙106 нм2 с описыванием окружностью пор при использовании программы, экспорт данных с вычис-лением радиальных размеров на поверхностном (активном) слое мембраны в нм. Посредством про-грамной функции AutoCad 2018 находяться главные характеристики (диаметр, площадь каждого эле-мента), затем определялся коэффициент засоренности. Для оценки погрешности определения размеров пор анализировали 5 электронных изображений, полученных для различных участков поверхности ис-следуемой мембраны. Процедуру обработки каждого электронного изображения повторяли 10 раз. В результате статистической обработки результатов относительное стандартное отклонение не превы-шало 0.1. С помощью функции описательной статистики программой Microsoft Excel 2010 определя-лись среднеквадратичное отклонение, средний диаметр пор и производилось построение гистограмм, графиков функции плотности распределения вероятностей и нормального распределения для исследу-емых мембран от распределения диаметров пор.Установлено, что распределение пор по диаметрам на поверхности активного слоя исследуе-мых ультрафильтрационных мембран описывается законом нормального распределения (закон Гаусса). Получены эмпирические выражения функции нормального распределения пор по диаметрам. Анализ экспериментальных исследований методом электронной микроскопии, стандартных средств обработки данных Microsoft Excel 2010, AutoCad 2018 показал, что для образцов мембран УАМ-50, УАМ-100, УПМ-К, УПМ-100 средний диаметр пор на поверхности находится в интервале от 54 до 70 нм

Апаратно-програмна реалізація інтелектуальної комп’ютерно-інтегрованої системи контролю та прогнозування величини струму витоку електрообладнання тваринницького приміщення

. The development of advanced protection systems and ways to reduce electricity losses during its transportation by power lines is an urgent scientific problem. The main source of leakage current in livestock facilities are electric motors, which are necessary to ensure the technological process. Humidity of the electric motor has an extremely negative effect on the condition of the motor insulation. The purpose of the study is to develop the structure of a computer-integrated system that monitors and predicts the values of motor leakage current to prevent its impact on animal living conditions and dangerous consequences for living organisms with hardware-software implementation of computer-integrated control system based on SCADA Trace Mode. T his article considers the possible hardware and software implementation of an intelligent computer-integrated control system and forecasting the value of the leakage current of electrical equipment of livestock premises. To provide automated real-time control, a SCADA system with appropriate software has been developed. This software is installed on computers and, to communicate with the object, uses I/O drivers or OPC/DDE servers. Program code can be written in a programming language (such as C++) or generated in an automated design environment. The modular product SCADA Trace Mode was used for technical and software implementation of the developed system. Key words: leakage current, SCADA, SCADA Trace Mode, control, network

Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis

Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis

Parallel Combinational Equivalence Checking

Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed, addressing different design and verification scenarios. The experimental results have demonstrated the speedups up to $63\times $ when comparing the proposed approach to a single-threaded implementation of a similar CEC engine. A practical impact of such a speedup, for instance, is the runtime reduction from 19 h to only 18 min when checking equivalence of AND-inverter graphs comprising more than 20 million nodes. Therefore, the proposed solution presents great potential for improving current electronic design automation environments.

A Systematic Equalizer Design Technique Using Backward Directional Design

This paper presents a systematic equalizer design methodology using a backward directional design (BDD). The proposed design method includes pre-emphasis and crosstalk cancellation design and offers a proper waveform solution for transmitters (TX). Since it is driven by a user-defined specification, it avoids over/under design, reducing wasted power. Furthermore, the proposed design procedure is summarized in systematic algorithms and provides an automated design environment. The procedure has been tested for various line conditions to verify the algorithms. The result shows that the proposed method successfully designs equalizers to within a 2.4% error.

Multiphysics Simulation of Biosensors Involving 3D Biological Reaction–Diffusion Phenomena in a Standard Circuit EDA Environment

The topic of this paper is the development of biological models for 3D reaction–diffusion phenomena that can be used in any circuit electronic design automation environment for the simulation of biosensors. Biological systems that involve such 3D phenomena are described by partial differential equations. Our approach consists in discretizing these equations according to the finite-difference method and converting the resulting ordinary differential equations into an assembly of elementary electronic equivalent circuits that are directly simulated with SPICE. The main interest of this approach is the ability to couple such models with third-party SPICE models of electronic circuits, sensors, and transducers, i.e., models from any physical domain ruled by Kirchhoff laws, allowing modeling and simulation of any multi-physics systems in a conventional circuit design environment, here CADENCE. The tool is validated on simple problems for which analytical solutions are known. Then, the interest of the approach is illustrated on the study of a biosensor.

PSK Transciever designing using SystemVue

Since, the industrial electronics is trending towards more compact components and system integration, innovative products offering greater flexibility, quality, safety, reliability, energy savings, wide range of connectivity with long operating lifetime. Now, Electronics is widely used in information processing, telecommunication and signal processing. Due to the complex nature of electronics theory, laboratory experimentation is an important part of development of electronic devices. These experiments are used to test or verify the proposed design and detect errors. Historically, electronics labs have consisted of electronic devices and equipment located in the physical space. Although in more recent years, the trend has been towards electronics lab simulation softwares and SystemVue is also one of them. SystemVue is a focussed electronic design automation (EDA) environment for electronic system-level (ESL) design. It enables system architects and algorithm developers to innovate the physical layer (PHY) of wireless and aerospace/defence communication systems and provide unique value to RF, DSP and FPGA/ASIC implementers. As a dedicated platform for ESL design and signal processing realization, SystemVue replaces general-purpose digital, analog and math environments. SystemVue “speaks RF”, cuts PHY development and verification time in half and connects to your mainstream EDA flow.

MEANS OF DYNAMIC DATA INTEGRATION IMPLEMENTATION VIA TOOLS OF EXISTING CAD SYSTEMS

Presented means of dynamic data integration implementation via tools of existing computer-aided design/drafting systems. When using design automation tools, the project documentation is interpreted as four aspects of the data representation: graphical, tabular, textual, mathematical. Demonstrated the possibility of developing software that provides dynamic integration of data on the proposed relational method in the automated design environment.

A tool for obtaining transparency and traceability in heterogeneous design automation environments

ABSTRACTToday, CAD-system are used for much more than just geometric modeling. They are complemented by various software and information sources forming a complete environment for handling all life-cycle aspects of the product. In such systems, the CAD-system works as a central hub. The software and information sources may be of various types making the system highly heterogenous. This presents problems with transparency and traceability in the system making long term management difficult. In this paper, a novel tool is presented to keep track of the dependencies between the various parts of such systems providing an overview and making it possible to predict the effect of proposed changes and facilitating long term management. The tool is tested in a highly heterogeneous environment at a manufacturer of aerospace components, with the result that the traceability is expected to increase at the expense of that time must be spent on defining dependencies and meta-information as the system is evolving.

Comparison between aerodynamic designs obtained by human driven and automatic procedures

In this paper a fast automatic design environment is developed, making use of a well established and validated turbomachinery design software system for geometry generation and flow analysis. The design is updated via a gradient based algorithm, where gradients are obtained using an adjoint method. The computational advantages of Graphics Processing Units are used to accelerate the mesh generation and flow analysis. The capabilities of the system are illustrated by automatically generating two Low Pressure Turbine vanes, and comparing them to the ones arrived at by a human designer, respecting the same explicit design criteria. The quality of the automatically designed airfoils is assessed against the human generated ones, and insight on the influence of implicit criteria is extracted. It is concluded that acceptable quality geometries can be designed automatically in a short time. For instance, the automatic procedure takes of the order of two days for an equivalent human driven case, where the designer took of the order of two weeks.

A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization

Sigma-Delta modulator (SDM) is a type of medium-speed but high-accuracy data converter. Signal-to-noise ratio (SNR) is one of its most critical design metrics. To enable automatic synthesis, fast SNR evaluation is of uttermost importance to accelerate the synthesis loop. In this paper a fast symbolic SNR computation method is proposed, which can automatically generate analytical SNR calculation formulas given a loop filter circuit design. Furthermore, Verilog-A implementation of this method is introduced, which demonstrates the feasibility of using the fast SNR computation method in a standard mixed-signal design automation environment. Application of the Verilog-A modules to SDM circuit optimization is demonstrated by invoking the build-in quasi-Newton optimizer in a Verilog-A tool and compared to the simulated annealing (SA) optimization. This work is an attempt of demonstration that a symbolic computation method can be integrated into a commercial mixed-signal design tool with good performance in behavioral synthesis. Utilization of the proposed method for behavioral Monte Carlo simulation in the Verilog-A environment was also found to be encouraging.

A surrogate-based integrated framework for the aerodynamic design optimization of a subsonic wing planform shape

Due to the development in computer technology, computational simulations have become indispensable for most engineering system design processes, particularly in aerospace applications. Performing a simulation-driven aerodynamic design optimization is a challenging task due to the computational expensiveness of high fidelity models, the considerable number of design parameters, the variety of disciplines that must be considered… etc. In this paper, the preliminary design of an aircraft wing through the use of a fully automated design environment, coupled with surrogate-based optimization, is presented. A parametric modeling framework was developed based on the seamless integration of several commercial software through built-in scripting languages. The design process goes through geometry modeling, Aerodynamic grid generation and flow solution which involves SIEMENS NX, ICEM CFD and FLUENT respectively. The optimization is made feasible using surrogate modeling techniques combined with a Sequential Quadratic Programing (SQP) algorithm.

Lightweight rotor design by optimal spar cap offset

Bend-twist coupling behavior is induced in a blade by displacing the suction side spar cap towards the leading edge, and the pressure side one in the opposite direction. Additional couplings are introduced by rotating the spar cap fibers. The structural configuration of the blade is optimized using an automated design environment. The resulting blade shows significant benefits in terms of mass and loads when compared to the baseline uncoupled one. Finally, the lightweight design concept is used to increase the rotor size, resulting in a larger energy yield for the same hub loads.

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.