Abstract

This paper presents a systematic equalizer design methodology using a backward directional design (BDD). The proposed design method includes pre-emphasis and crosstalk cancellation design and offers a proper waveform solution for transmitters (TX). Since it is driven by a user-defined specification, it avoids over/under design, reducing wasted power. Furthermore, the proposed design procedure is summarized in systematic algorithms and provides an automated design environment. The procedure has been tested for various line conditions to verify the algorithms. The result shows that the proposed method successfully designs equalizers to within a 2.4% error.

Highlights

  • The data transfer rate of integrated circuits is increasing [1]

  • The high-frequency energy loss and coupling in channels can be reduced by employing pre-emphasis [2,3,4,5,6], decision feedback equalizer [6,7], and crosstalk cancellation (XTC) [8,9,10], but there remains a problem of designing these circuits

  • A multi-line equalizer design cannot proceed with the same process that is applied to the single-line

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Summary

Introduction

The data transfer rate of integrated circuits is increasing [1] In these systems, signal loss and coupling effects can deteriorate a channel’s performance. Since there are many different kinds of interconnection in chip systems, a variety of equalizers must be designed to fit their application This is very complex work, requiring engineers to check specification, power, noise, and area. The backward directional design (BDD) process determines the desired output waveform first and it minimizes energy waste, implementing an equalizer with low power consumption. A systematic equalizer design methodology based on a BDD method is proposed. It provides more feasible waveforms and more efficient design procedures than previous approaches.

Conventional Backward Directional Design Method
Conventional
New DBB Design Technique
Waveform Determination in a Single Line
The high-frequency
V desired
Equalizer Design for a Single-Line Data Link
Equalizer
Line three-coupled extracted using
Design
Single
Gbps and
The similarity between the two
11. Comparison
Multi-Line
L 20uA are 6 k
Conclusions
Full Text
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