Atomistic Device Simulations Research Articles

Theoretical Optimization of an Earth-Abundant and Environmentally Friendly Photovoltaic Absorber Cu3PSe4 from First-Principles Study to Device Simulation.

To seek an earth-abundant and environmentally friendly absorber for thin-film solar cells, Cu3PSe4 is investigated by first-principles calculations and device simulations. We demonstrate that the compound has a suitable band gap width of 1.3 eV as well as a high sunlight absorption coefficient. However, drawbacks like small electron affinity, high hole concentration, large lattice mismatch with CdS, etc., are revealed, which may degrade the photovoltaic performance. To address those shortcomings, we propose (1) to optimize the carrier concentration by preparing the samples at low temperature and under a Cu-rich environment, (2) to replace the CdS buffer layer by a more suitable wide-gap semiconductor with smaller lattice mismatch, and (3) that the selected buffer layer should have small electron affinity in order to reduce the open-circuit voltage losses. After implementation of these optimization approaches, the device simulations demonstrate that the power conversion efficiency reaches 17.7% for a solar cell with the configuration Mo/Cu3PSe4/WS2/n-ZnO. The combination of first-principles calculations at the atomistic level and device simulations at the macroscopic level provides an appropriate approach to design ideal solar cells.

금속-산화막-반도체 전계효과 트랜지스터의 불순물 분포 변동 효과에 미치는 이온주입 공정의 영향

본 연구에서는 금속-산화막-반도체 전계효과 트랜지스터의 불순물 분포변동 효과에 미치는 halo 및 LDD 이온주입 공정의 영향을 3차원 소자 시뮬레이션을 통하여 확인하였다. 정확한 시뮬레이션 계산을 위해 kinetic monte carlo 모델을 적용하여 불순물 입자와 결함 낱낱의 거동을 계산하는 원자단위 시뮬레이션을 수행하였다. 문턱전압 및 on-current의 산포를 통해 확인한 결과 halo 이온주입 공정이 LDD 이온주입 공정보다 문턱전압 산포의 경우 약 6.45배 그리고 on-current 산포의 경우 2.46배 더 큰 영향을 미치는 특성을 확인하였다. 그리고 문턱전압과 on-current 산포를 히스토그램으로 나타내어 그 산포를 정규분포로 확인하였다. In this study the influence of the random dopant fluctuation (RDF) depending on the halo and LDD implantations for the metal-oxide-semiconductor field effect transistor is investigated through the 3D atomistic device simulation. For accuracy in calculation, the kinetic monte carlo method that models individual impurity atoms and defects in the device was applied to the atomistic simulation. It is found that halo implantation has the greater influence on RDF effects than LDD implantation; three-standard deviation of <TEX>$V_{TH}$</TEX> and <TEX>$I_{ON}$</TEX> induced by halo implantation is about 6.45 times and 2.46 times those of LDD implantation. The distributions of <TEX>$V_{TH}$</TEX> and <TEX>$I_{ON}$</TEX> are also displayed in the histograms with normal distribution curves.

Surface Passivation in Empirical Tight Binding

Empirical Tight Binding (TB) methods are widely used in atomistic device simulations. Existing TB methods to passivate dangling bonds fall into two categories: 1) Method that explicitly includes passivation atoms is limited to passivation with atoms and small molecules only. 2) Method that implicitly incorporates passivation does not distinguish passivation atom types. This work introduces an implicit passivation method that is applicable to any passivation scenario with appropriate parameters. This method is applied to a Si quantum well and a Si ultra-thin body transistor oxidized with SiO2 in several oxidation configurations. Comparison with ab-initio results and experiments verifies the presented method. Oxidation configurations that severely hamper the transistor performance are identified. It is also shown that the commonly used implicit H atom passivation overestimates the transistor performance.

Tight-binding analysis of Si and GaAs ultrathin bodies with subatomic wave-function resolution

Empirical tight binding(ETB) methods are widely used in atomistic device simulations. Traditional ways of generating the ETB parameters rely on direct fitting to bulk experiments or theoretical electronic bands. However, ETB calculations based on existing parameters lead to unphysical results in ultra small structures like the As terminated GaAs ultra thin bodies(UTBs). In this work, it is shown that more reliable parameterizations can be obtained by a process of mapping ab-initio bands and wave functions to tight binding models. This process enables the calibration of not only the ETB energy bands but also the ETB wave functions with corresponding ab-initio calculations. Based on the mapping process, ETB model of Si and GaAs are parameterized with respect to hybrid functional calculations. Highly localized ETB basis functions are obtained. Both the ETB energy bands and wave functions with subatomic resolution of UTBs show good agreement with the corresponding hybrid functional calculations. The ETB methods can then be used to explain realistically extended devices in non-equilibrium that can not be tackled with ab-initio methods.

Empirical tight binding parameters for GaAs and MgO with explicit basis through DFT mapping

The Empirical Tight Binding (ETB) method is widely used in atomistic device simulations. The reliability of such simulations depends very strongly on the choice of basis sets and the ETB parameters. The traditional way of obtaining the ETB parameters is by fitting to experiment data, or critical theoretical bandedges and symmetries rather than a foundational mapping. A further shortcoming of traditional ETB is the lack of an explicit basis. In this work, a DFT mapping process which constructs TB parameters and explicit basis from DFT calculations is developed. The method is applied to two materials: GaAs and MgO. Compared with the existing TB parameters, the GaAs parameters by DFT mapping show better agreement with the DFT results in bulk band structure calculations and lead to different indirect valleys when applied to nanowire calculations. The MgO TB parameters and TB basis functions are also obtained through the DFT mapping process.

Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants

A new methodology for circuit level transient simulation of Random Telegraph Noise (RTN) is proposed. The physically based methodology properly models the microscopic phenomena involved in RTN, including their stochastic nature. Using a modified BSIM code, the compact model is implemented in a SPICE simulator, accounting for non-stationary RTN effects under arbitrary bias. The probability of traps to capture or emit charge carriers is updated at each time step of the transient simulation according to the actual bias conditions of the device. Atomistic device simulations are performed in order to study the impact of trap position along the channel on the amplitude of the contribution of a trap to RTN. These device simulations take into account short-range Coulomb interactions and show the relevance of large local deviations of mobility values of carrier electrons, particularly for traps near the source end of the channel. As a case study, jitter in an oscillator is simulated. It is shown that the methodology properly addresses open issues in the literature, by properly accounting for bias-dependent, non-stationary statistic of RTN phenomena relevant to the design of integrated circuits.

Impact of Individual Charged Gate-Oxide Defects on the Entire $I_{D}$–$V_{G}$ Characteristic of Nanoscaled FETs

The measurement of the entire ID-VG characteristic of a nanoscaled pMOSFET before and after the capture of a single elementary charge in a gate-oxide defect is demonstrated. The impact of a single trapped carrier on the device characteristics is compared with 3-D atomistic device simulations. The ID-VG behavior is identified to depend on the location of the oxide defect with respect to the critical spot of the current percolation path in the channel.

Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.

Exploring doping options and variability of trigate transistors using atomistic process and device simulations

This work explores several options for the channel-stop implant and source/drain doping for bulk trigate transistors using three-dimensional atomistic simulation. Considering tight silicon fin spacing and difficulty of using conventional ion implantation for the source/drain doping, the authors model both the implantation and plasma doping options. Considering the size of silicon fin and a handful of dopant atoms at play, the kinetic Monte Carlo approach offers a natural way of investigating atomistic effects and device variability. Atomistic device simulation provides an insight into the impact of different doping options on performance and variability of the trigate transistors. The provided insight is instrumental in selecting the best doping options and optimizing the tradeoff between performance and variability.

Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET

A study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFET versus the planar bulk MOSFET is performed via atomistic 3D device simulation for devices with a 20 nm gate length. For identical nominal body and source/drain doping profiles and layout width, the trigate bulk MOSFET shows less threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) lowering and variation. RDF effects are found to be caused primarily by body RDF. The trigate bulk MOSFET offers a new method of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> adjustment, via tuning of the retrograde body doping depth, to mitigate tradeoffs in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variation and short-channel effect control.

FinFET Design for Tolerance to Statistical Dopant Fluctuations

Variations in highly scaled (L G = 9 nm), undoped-channel FinFET performance, caused by statistical dopant fluctuations (SDFs) in the source/drain (S/D) gradient regions, are systematically investigated using 3-D atomistic device simulations. The impact of SDF on device design optimization is examined and simple design strategies are identified. Variation-tolerant design imposes stringent specifications for S/D lateral abruptness and gate-sidewall spacer thickness, and it poses a tradeoff between performance and variability for body thickness.

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13 and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' atomistic device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: in the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values

Impact of scattering in ‘atomistic’ device simulations

In this paper, by comparison of Drift-Diffusion and Monte Carlo simulation results, we investigate the impact of Coulombic scattering in atomistic device simulations and its contribution to the random dopant induced intrinsic parameter fluctuations in nano-CMOS devices. By introducing ionised impurity scattering directly into the Monte Carlo simulations through the full impurity potential, we resolve the contribution of the variation in scattering on the random dopant induced current variation. In comparison, Drift-Diffusion simulations are only able to capture the corresponding electrostatic effects. This approach is first demonstrated for the simple case of a single scattering centre in the channel of a MOSFET and then used to compare current variations in a set of devices with atomistic doping.