Three-dimensional integrated circuit (3D IC) packaging offers significant advantages, such as enhanced computational efficiency through greater integration and shorter interconnection distances. The effective interconnection of layers, particularly through redistribution layer (RDL) technology, is crucial for the successful operation of 3D ICs. While copper remains the preferred material for interconnections, often in conjunction with through-silicon via (TSV) technology for chip-to-chip links, the shrinking dimensions of components present challenges. In particular, the reduction in size may lead to elevated current densities in individual joints, giving rise to issues like electromigration (EM) and potential failure. EM-induced atomic migration may lead to the formation of voids in the interconnection. The accumulation of voids to a critical point may result in an open circuit in the joints, significantly impacting the conductor's reliability. This work delves into the micro-scale aspects of these challenges, complementing previous macroscopic investigations. We aim to elucidate the behavioral mechanisms through atomic-scale observations, employing an in-situ high-resolution transmission electron microscope (in-situ HRTEM) to observe atomic-scale images of EM. The insights gained from this work not only contribute to the academic understanding of industry challenges but hold potential applications in real-world manufacturing processes. Fig. 1. (a) Schematic diagram of TEM sample preparation. (b) Cross-sectional HRTEM image of copper bonding. (c, d) TEM images showing voids expansion at bonding interface. Figure 1