Asynchronous Transfer Mode Switching System Research Articles

An efficient cell-scheduling algorithm for multicast ATM switching systems

We propose an efficient multicast cell-scheduling algorithm, called multiple-slot cell-scheduling algorithm, for multicast ATM switching systems with input queues. Cells in an input-queueing system are usually served based on the first-in-first-out (FIFO) discipline, which may have a serious head-of-line (HOL) blocking problem. Our algorithm differs from previous algorithms in that we consider the output contention resolution for multiple time slots instead of the current time slot only. Like a window-based scheduling algorithm, our algorithm allows cells behind an HOL cell to be transmitted prior to the HOL cell in the same input port. Thus, HOL blocking can be alleviated. We have illustrated that the delay-throughput performance of our algorithm outperforms most of those algorithms that consider only the output contention resolution for the current time slot. We also present a simple and efficient architecture for realizing our algorithm, which can dramatically reduce the time complexity. We believe that the proposed architecture is very suitable for multicast asynchronous transfer mode (ATM) switching systems with input queues.

A compact optical active connector: an optical interconnect module with an electrical connector interface

This paper describes a compact optical active connector that has both optical and electrical interfaces for an asynchronous-transfer-mode (ATM) switching system and high-speed computer network systems. This connector with an O/E or E/O conversion module can replace the conventional electrical-cable six-pin connector for an ordinary printed circuit board that has only an electrical interface. Our connector consists of a specially developed duplex MU-type submodule with photonic devices, an electrical connector, and integrated circuits (ICs). It can be used for 620-Mbps data transmission and has lower electromagnetic radiation noise than conventional connectors. Using optical active connectors to replace electrical-cable connectors will facilitate the introduction of high-throughput, large-capacity ATM switching systems, and next-generation local area network systems.

Minimizing call setup delay in ATM networks via optimal processing capacity allocation

This paper considers the problem of process allocation in designing real-time call setup for asynchronous transfer mode (ATM) networks. With the constraint of finite processing capacity in a realistic ATM switching system, we aim to minimize the call setup delay by avoiding the potential bottleneck process. Our approach is to distribute and balance the processing loads among call control processes via optimal capacity allocation. The derived results can provide important and useful guidelines in system design and performance evaluation.

Breakthrough technologies for the high-performance electrical ATM switching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 /spl mu/m bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8/spl times/8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems.

A simple bandwidth management strategy based on measurements of instantaneous virtual path utilization in ATM networks

A new connection admission control method based on actual virtual path traffic measurements is proposed to achieve high bandwidth efficiency for various types of traffic. The proposed method is based on the measurement of instantaneous virtual path utilization, which is defined as the total cell rate of the active virtual channels normalized by the virtual path capacity. A low-pass filter is used to determine the instantaneous virtual path utilization from crude measurements. A smoothing coefficient formula is derived as a function of the peak rate of the virtual channel. The residual bandwidth is derived from the maximum instantaneous utilization observed during a monitoring period. Simulation shows that the proposed method achieves statistical multiplexing gains of up to 80% of the limit possible with optimum control for similar traffic sources. It can be implemented with very simple hardware. The admission decision is simple: the requested bandwidth is compared with the residual bandwidth. This method is therefore well suited for practical asynchronous transfer mode switching systems.

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.

The barrel switch: An ATM switch architecture for high‐speed switching

AbstractThis paper proposes a new asynchronous transfer mode (ATM) switch architecture called a “barrel switch.” The barrel switch is constructed from n/2 × n identical element switches which are placed out around a cylinder and connected to each other.The features of this proposed switch are as follows.1. This switch has an architecture suitable for high‐speed (2.4 Gbps and more) cell switching.2. It is a multistage self‐routing and nonblocking switch.3. Copy connections can be realized with this switch.4. The building‐block method is applicable to switch implementation, which ensures a full scalability.Cell loss rate and delay characteristics of this switch also are discussed using computer simulation results. Simulation results under random traffic prove that a 64 × 64 barrel switch has adequate cell loss rate and mean delay characteristics to an actual ATM switching system.

Management and control functions in ATM switching systems

As research has progressed, it has become clear that the main difficulties in ATM pertain to its operational details rather than the concept. And it seems likely that these control issues will be much more complicated and costly for ATM switches when compared with current telephone circuit switches. The asynchronous transfer mode (ATM) is the target switching technique for the future public broadband integrated services digital network (B-ISDN). The purpose of this article is to examine the management and control functions in ATM switching systems implied by current industry standards and agreements on OAM and traffic control. Until now, ATM research in the areas of switch design and traffic control have progressed essentially independently. First, we briefly review the B-ISDN Protocol Reference Model and its representation of the different information flows in ATM. Network management and traffic control principles in ATM, and in particular OAM, are overviewed. With this information as background, we attempt to infer their implications on the functional blocks of an ATM switching system. An example switch architecture model with distributed management and control functions is outlined, and some design issues are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Terahipas: a modular and expandable terabit/second hierarchically multiplexing photonic ATM switch architecture

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's). >

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8- mu m BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8*8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing. >

Architectures for ATM switching systems

Eight specific architectures for asynchronous transfer mode (ATM) switching systems are compared: the Knockout, Sunshine, Lee's, Tandem Banyan, Shuffleout, and three variations on buffered Benes networks. The differences between switching systems, based on architectural choices rather than details of implementation are discussed. Several broad categories of systems based on high-level architecture choices are considered. Within each category one or more alternatives are reviewed, and an equation for the chip count for each alternative is developed. The equations are used to make plots of chip count for each network over a range of parametric values. >

An ATM switch hardware technologies using multichip packaging

An asynchronous transfer mode (ATM) switching system constructed of copper-polyimide multilayer multichip modules (MCMs) is described. High throughput ATM switching systems require high-speed interconnections and high-density packaging to reduce the interconnection lengths. An ATM prototype switching system which consists of two ATM switch MCMs was developed. The ATM switch MCM contains 24 LSIs and a multilayer substrate with polyimide dielectric and a fine pattern copper conductor. A fine pitch flexible lead 680-way connector was developed to achieve a high-speed interconnection between the MCM and printed circuit board. Tap automated bonding (TAB) was used to allow pretesting of the LSI devices and to mount high pin count LSI devices onto the MCM. The system performed 16*16 ATM cell switching at 150 Mb/s. Furthermore, it transmitted NRZ signals of up to 810 Mb/s between MCMs via fine-pitch flexible lead connectors and a 40-cm line in the printed circuit board.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Practical implementation and packaging technologies for a large-scale ATM switching system

The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-throughput cell scheduling for broadband switching systems

The authors consider the output contention problem with a view towards increasing the throughput for asynchronous transfer mode (ATM) switching systems. A cell scheduling algorithm for increasing the throughput is proposed. The maximum throughput is increased up to 0.957. The efficiency (output trunk utilization/input trunk utilization) is almost equal to 100% and is independent of the switch size and traffic load. A switching system implemented with this cell scheduling algorithm is also proposed. The switching network usually consists of a sorting network followed by a routing network. Here, it is sufficient for a sorting network to establish input-output paths through it simultaneously without conflicts, and it is not necessary to append a routing network. In addition, a parallel mesh-connected architecture of a component of the switching system is proposed to speed up the cell scheduling of the system. Consequently, this approach can offer an effective alternative to ATM switching systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers. >

Considerations in ATM switching system traffic control

AbstractWe propose a traffic control scheme for asynchronous transfer mode (ATM) switching systems, clarifying requirements for traffic control derived from the ATM network characteristics and demonstrating basic control concepts. The proposed scheme accepts calls based on the available bandwidth and buffer use rate, making it possible to integrate the network without classification by service type.