ATM Switching Element Research Articles

Performance Analysis of Multiserver ATM Buffers Routing Multimedia Traffics with Geometric Service Time

In this article we analyze the performance of discrete-time multiserver ATM buffers with batch arrivals, geometric service time and priority scheduling. Such systems can be applied to the detailed performance evaluation of ATM multiplexers and ATM switching elements with dedicated buffer output queuing arrangements. Packets belong to two classes, class-1 packets represents real time traffics which is delay sensitive but loss insensitive, and class-2 packets represents non real time traffics which is delay insensitive but loss sensitive. Higher service priority is given to real time traffics (e.g. audio and video) to respond to the delay sensitivity in the presence of multiple servers in the system. Expressions for the probability generating functions of the main performance measures of the system and expected values of these expressions are evaluated.

Performance Analysis of Multiserver ATM Buffers Routing Multimedia Traffics with Geometric Service Time

In this article we analyze the performance of discrete-time multiserver ATM buffers with batch arrivals, geometric service time and priority scheduling. Such systems can be applied to the detailed performance evaluation of ATM multiplexers and ATM switching elements with dedicated buffer output queuing arrangements. Packets belong to two classes, class-1 packets represents real time traffics which is delay sensitive but loss insensitive, and class-2 packets represents non real time traffics which is delay insensitive but loss sensitive. Higher service priority is given to real time traffics (e.g. audio and video) to respond to the delay sensitivity in the presence of multiple servers in the system. Expressions for the probability generating functions of the main performance measures of the system and expected values of these expressions are evaluated.

Performance improvement of dynamic buffered ATM switch

Performance of ATM networks depends on switch performance and architecture. This paper presents a simulation study of a new dynamic allocation of input buffer space in ATM switching elements. The switching elements are composed of input and output buffers which are used to store received and forwarded cells, respectively. Efficient and fair use of buffer space in an ATM switch is essential to gain high throughput and low cell loss performance from the network. In this paper, input buffer space of each switching element is allocated dynamically as a function of traffic load. A shared buffer pool is provided with threshold-based virtual partition among input ports, which supplies the necessary input buffer space as required by each input port. The system behaviour under varying traffic loads has investigated using a simulation program. Also, a comparison with a static allocation scheme shows that the threshold based dynamic buffer allocation scheme ensures an increased network throughput and a fair share of the buffer space even under bursty loading conditions.

Rare event analysis of the state frequencies of a large number of Markov chains

This paper focuses on the situation of a large number n of i.i.d. Markov chains. The fractions of these n Markov chains being in any specific state are called state frequencies (or:‘empirical distribution’). We provide a large deviations analysis of the probability of these state frequencies reaching a distribution β from a given initial distribution α in a fixed amount of time t. This probability is characterizered asymptotically in the number of Markov chains. Apart from these asymptotics, it is also shown how the rare event occurs: the ‘most likely path’ from α to β in t units of time is explicitly calculated. It is argued that the analysis provides useful insight into the likelihood of extreme fluctuations of the input rate of an ATM switching element or an IP router. A number of numerical examples are included

Wireless ATM LAN with and without infrastructure

We consider wireless ATM concepts for small LANs, especially for SOHO and future consumer applications. We describe a wireless ATM LAN framework architecture that supports wireless ATM communications in environments with and without fixed ATM infrastructure. For the configuration with an ATM infrastructure, a distributed ATM switched backbone is proposed, which enables a smart ATM switching element to be embedded in every wireless and fixed access point. For bandwidth efficiency and ease of operation (place-and-play), we also propose an ad hoc wireless ATM LAN concept based on the same 5 GHz wireless ATM air interface as is currently under standardization in the ETSI/BRAN and ATM Forum. Unlike CSMA-based ad hoc systems such as HIPERLAN and IEEE802.11, our ad hoc wireless ATM system makes QoS management feasible in an infrastructureless environment by using resource reservation and scheduled medium access protocol. Since cost scalability is essential throughout our system design, we consider forwarding between ad hoc subnets and interworking with the fixed network as important but optional features.

Letter: ATM switches with nonindependent routing

AbstractAn N × N ATM switching element with output queueing is considered. Each inlet of the switch is fed by a bursty on/off source with geometrically distributed on/off‐periods. Cells are routed from the inputs to the outputs of the switch in a uniform but correlated manner. Specifically, for the first cell of each on‐period all the destination addresses are equiprobable. Each subsequent cell of the same on‐period has a probability R of being routed to the same destination as the previous cell, and is sent to one of the N‐ 1 other destinations with probability (1 ‐ R)/(N ‐ 1). Cells belonging to different on‐periods are routed entirely independently. By means of an approximate analytical method, the influence of the degree of burstiness of the sources and the amount of correlation in the routing mechanism on the queueing performance of the switch is investigated.

Storage requirements in ATM switching elements with correlated arrivals and independent uniform routing

An ATM switching element with a finite number of independent and identical traffic sources (users), and an equally high number of destinations is considered. The sources are assumed to be bursty, and the burstiness of the sources is modeled by describing both their active periods (during which users generate one cell per slot) and their passive periods (during which users do not generate data) as geometric random variables. Arriving cells are assumed to be routed to their destinations in a uniform and independent way. As a result, a correlated-arrivals queueing model for the switch is obtained, which is analyzed in this paper by purely analytical means. Specifically, closed-form expressions for the mean and the variance of the buffer contents, and an accurate analytic approximation for the tail probabilities of the buffer contents are derived.

An approximate analytical technique for the performance evaluation of ATM switching elements with burst routing

In this paper we consider an ATM (Asynchronous Transfer Mode) switching element with output queueing. One separate infinite-capacity output buffer is used for each possible destination (output). The cell arrival processes on the inlets of the switching element are of a bursty nature. Specifically, geometrically distributed on/off-periods are assumed to describe this burstiness. Cells are routed from the inputs to the outputs of the switching element in a uniform but correlated manner, i.e., all cells belonging to the same on-period are routed to the same destination, but all destinations are equiprobable. The queueing performance of the switch is analyzed here by a combination of analytic techniques and approximations. Close analytic upper bounds are obtained for such measures as the means and the tail distributions of the buffer contents and the cell delay in a tagged output buffer. The formulas are easy to evaluate and the results are useful in practice, for instance, to calculate the cell loss ratio or the delay jitter in an output queue. The influence of the degree of burstiness in the cell arrival processes is investigated. Also, the results are compared with the case of uncorrelated routing.

Performance evaluation of multipoint cellbuffering in ATM

The Letter presents results relating to the replication of multipoint (MP), sometimes called multicast, cells in an ATM switching element. Specifically, two stratagies are evaluated for mean delay and cell loss probability (CLP).

Optimal flow control of a stochastic fluid-flow system

This paper is concerned with the optimal flow control of an ATM switching element in a broadband-integrated services digital network. We model the switching element as a stochastic fluid-flow system with a finite buffer, a constant output rate, and Markov-modulated fluid input. There is a cost of holding fluid and a reward for admitting the fluid to the buffer. We study the optimal flow control policies that minimize the fetal expected discounted cost. We analyze the problem by two different approaches and show that the optimal policy is of the turnpike type with the turnpike levels dependent on the states of the Markov-modulated source. We also state sufficient conditions under which the optimal turnpike levels are monotonic functions of the states of the Markov-modulated source. >

Analytic derivation of tail probabilities for queue lengths and waiting times in ATM multiserver queues

In this paper we consider a discrete-time queueing model, useful for the design and the performance evaluation of many slotted communication system in general, and ATM-based networks in particular. The model assumes a general independent packet arrival process, an infinite waiting room, and an arbitrary number of servers. By means of an approximation technique, explicit closed-form expressions are derived for the tail probabilities of both the buffer contents (queue length) and the delay (or the waiting time). These formulas are very easy to evaluate. They are applied in the performance analysis of an ATM switching element with output queueing, in order to obtain predictions for such quantities as the cell loss ratio and the delay jitter. Also, an application with more bursty arrivals is discussed. In both cases, very good agreement between actual (numerical) and approximate (analytic) results is observed.

Analysis of discrete-time multiserver queueing models with constant service times

A discrete-time multiserver queueing model is analyzed. The model allows for an arbitrary number of servers, arbitrary-length constant service times, and general independent arrivals. As a result of the analysis, an explicit expression is obtained for the generating function of the queue length, which easily allows the derivation of such performance measures as the moments and the tail distribution of the queue length. Application areas of the model include ATM switching elements, circuit-switched TDMA systems and traffic concentrators.

Performance evaluation of an M/1-stage in an ATM switching element

The M/1-stage studied in this paper consists of M incoming lines who share a bus for the transmission of packets to an outgoing line. The capacity of the bus is δ times higher than the speed of the incoming lines. The internal buffering is achieved by a common output buffer at the end of the bus, and by providing the crosspoints with small input buffers. The system is modeled as a finite capacity multi-queueing system with non-renewal input and cyclic non-exhaustive service discipline. The input processes belong to a class of tractable Markovian arrival processes (MAPs) introduced by Lucantoni, Meier-Hellstern and Neuts (1990), allowing the model to include bursty input traffic. Each buffer in the system is studied approximately by means of a finite capacity queue with repeated server vacations and limited service discipline, resulting in several performance measures of the system: the queue length distribution at an arbitrary time instant and at arrival instants for each queue, the loss probability of an arriving cell, the LST of the waiting time of an arriving cell. These results can be used to chose an optimal value for the factor δ, together with an accurate dimensioning of the buffers in the M/1-stage, in order to minimize the chip size and such that the required performances (cell delay, delay jitter, cell loss) are guaranteed.

Gauss: a simple high performance switch architecture for ATM

Broadband ISDN will use the Asynchronous Transfer Mode (ATM) as its basic switching, multiplexing and transmission technique. ATM is very flexible and promising, nevertheless, it requires high-performance switching hardware. The ATM Switching Element (ASE) proposed in this paper, called the Gauss ASE, can meet ATM requirements. Using traffic observations and a number of well known design principles the Gauss ASE gets a number of favorable properties, for example the Gauss ASE is nonblocking and has minimum delay and variance of delay. The ASE is kept modular so that it can easily grow towards a large single stage switching fabric using only two types of Integrated Circuits.

Buffer sizing in an ATM switch for both ATM and STM traffics

AbstractSpecific queueing models are derived in order to size the buffers of ATM switching elements in the cases of ATM or STM multiplexed traffic. Buffering is performed either at the outputs or in a central memory for ATM multiplexed traffic; for STM multiplexed traffic, buffers can also be provided at the inputs. The buffer size is chosen in order to ensure a loss probability in the switch smaller than 10−10.It is shown that the buffer size per output in the case of central queueing is smaller than the buffer size in case of output queueing for both ATM and STM multiplexed traffics. Moreover, for STM multiplexed traffic, buffer sizes are identical for input and output queueing. Lastly, it is pointed out that buffers used for STM multiplexed traffic should be 4 to 20 times larger than the corresponding buffers for ATM multiplexed traffic.