This paper provides a methodology to decompose a complex network, containing primarily deterministic traffic, into isolated /spl Sigma/D/sub i//D/1 queuing models. We then present a new technique, Successive Superposition, to analyze the resulting models. In a /spl Sigma/D/sub i//D/1 queuing system, multiple streams of different bit rate, but constant length packets, arrive at a single high-speed multiplexer. Because of its application to Asynchronous Transfer Mode (ATM) switching nodes, previous /spl Sigma/D/sub i//D/1 analyses have assumed that stream arrivals are randomly staggered, and packets are served on a first-come-first-served basis. This work was, however, inspired primarily by the need for the accurate assessment of interprocessor communication costs in compile-time multiprocessor scheduling applications. For these applications, streams typically have known arrival times and must often be prioritized. This paper applies primarily to the class of digital signal processing and other application which can be represented by directed, acyclic precedence graphs. The analysis presented in this paper provides an exact characterization of the traffic, including service start times, queue sizes, and system departure times. We confirm the validity of our approach against simulation results. Finally, we demonstrate the utility of this work in a compile-time multiprocessor scheduling application.