Asynchronous Successive Approximation Register ADC Research Articles

A Compact Fully Dynamic Capacitance-to-Digital Converter With Energy-Efficient Charge Reuse

An ultra-low-power fully dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed. The CDC includes a capacitive bridge as the sensing frontend and an asynchronous successive approximation register ADC for signal digitization. Passive charge sharing between the frontend and ADC is used to enable a fully dynamic operation. Instead of resetting the capacitive bridge (with large sensing and reference capacitors) for each measurement, the charge is maintained and reused over many measurements to save energy. A power-gating technique is employed to reduce the stand-by power. As a result, a figure of merit as low as 4.3 fJ/conv-step is achieved for the CDC, which is >3× better than the state of the art. Furthermore, it supports an inherent scaling of power versus speed with a minimum power of only 44 pW and a compact chip area of 6440 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 nm CMOS. The ADC occupies 0.054 mm2 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.

An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 μm CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the on-chip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv·step, excluding the reference's power consumption.