Abstract
An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 nm CMOS. The ADC occupies 0.054 mm2 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.
Highlights
From low speed applications such as industrial monitoring, bio-medical and sensor node [1,2,3] to high speed applications such as high speed links and generation communication systems [4,5], Successive Approximate Register (SAR) ADC is the most widely adopted ADC architecture owing to its low power operation from a simple operating principle
An asynchronous architecture is widely used to mitigate the requirements of the comparison time of the comparator in SAR ADC
This paper focuses on digitally controlled delay generation methods with linear delay characteristics when the asynchronous SAR ADC has a sampling frequency of several MS/s
Summary
From low speed applications such as industrial monitoring, bio-medical and sensor node [1,2,3] to high speed applications such as high speed links and generation communication systems [4,5], Successive Approximate Register (SAR) ADC is the most widely adopted ADC architecture owing to its low power operation from a simple operating principle. This paper focuses on digitally controlled delay generation methods with linear delay characteristics when the asynchronous SAR ADC has a sampling frequency of several MS/s. An MOS transistor array was used as a variable resistor Another method used to generate a digitally controlled delay cell is a current starved architecture [10]. Transistor array was used as a variable resistor
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