Asynchronous Router Research Articles

An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-on-chips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves % chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics.

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are 0.93 μW/core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art.

A Scheduled Based Argo NI NoC Using GALS Architecture for MPSOC

In this paper, we have designed and implemented a scheduling for the micro-architecture of Argo Network Interface (NI), works based on globally asynchronous and locally synchronous (GALS) which provides efficient area for a real time multiprocessor application platform and uses time division multiplexing for message passing between the multiprocessor cores. Statically scheduled TDM controls the network on chip structure to provide the guarantee over the real time multiprocessor application. GALS architecture contributes asynchronous routers collaborates scheduling and micro architecture together and results the data transformation in pipelined fashion from sending core to the receiving core of the local memory with none dynamic arbitration, clock synchronization and buffering. NI combines functionality of DMA, TDM and double ported memories to overcome from synchronization, buffering and control of flow rate. To substantiate the planning they have executed four-by-four bits in 65nm NoC CMOS mechanism then represented results on energy deletion, area and the speed for router, network on chip, post layout and network interface. Scheduling is done based on the resources like flit size, bandwidth, energy depletion etc., has been implemented. As a result the reliability of the argo NoC is elevated for more hard real-time applications.

Performance analysis of asynchronous priority-based internet router under self-similar traffic input - queueing system with Markovian input and hyper-exponential services

In this paper, queueing behaviour of asynchronous priority-based internet router with self-similar traffic input is analysed. As Markov modulated Poisson process (MMPP) emulates self-similar traffic, it is used as input process of pertinent queueing system. For quality of service (QoS) guarantee in a broadband integrated services digital network (B-ISDN), partial buffer sharing (PBS) mechanism is promising one. Since, network traffic is asynchronous and of variable packet lengths, wavelength division multiplexing (WDM) technology is to be employed, according to which, each output port is modelled as multi server queueing system. The service times (packet lengths) are assumed to follow hyper-exponential (Hk) distribution. For the said reasons, router here is modelled as MMPP/Hk/s/C queueing system employing PBS mechanism. High and low priority packet loss probabilities, and mean lengths of non-critical and critical periods are computed, and presented graphically. This analysis is useful in dimensioning the priority-based asynchronous router with self-similar traffic input.

Performance analysis of asynchronous priority-based internet router under self-similar traffic input - queueing system with Markovian input and hyper-exponential services

In this paper, queueing behaviour of asynchronous priority-based internet router with self-similar traffic input is analysed. As Markov modulated Poisson process (MMPP) emulates self-similar traffic, it is used as input process of pertinent queueing system. For quality of service (QoS) guarantee in a broadband integrated services digital network (B-ISDN), partial buffer sharing (PBS) mechanism is promising one. Since, network traffic is asynchronous and of variable packet lengths, wavelength division multiplexing (WDM) technology is to be employed, according to which, each output port is modelled as multi server queueing system. The service times (packet lengths) are assumed to follow hyper-exponential (Hk) distribution. For the said reasons, router here is modelled as MMPP/Hk/s/C queueing system employing PBS mechanism. High and low priority packet loss probabilities, and mean lengths of non-critical and critical periods are computed, and presented graphically. This analysis is useful in dimensioning the priority-based asynchronous router with self-similar traffic input.

PANE

Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the P luggable A synchronous NE twork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations—routing algorithms, topologies, network sizes, and so on—for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC

Recently, there has been enormous attention given to the network on chip (NoC) because it is scalable compared to the communication bus. Three dimensional (3D) NoC is getting more popular due to the reduction of wire length with that off two dimensional NoC. The router in the NoC is provides communication between the different computational units. In this paper, a two-phase bundled-data handshake latch is used with an asynchronous router. The Mousetrap latch controller forms the basis of this asynchronous router. The major part of the arbiter is to schedule the packet, then deliver to its destination without any loss of the packet. This paper proposes a novel asynchronous 3D lottery routing algorithm which is based on arbitral mechanism. The Lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The proposed hardware is implemented using Cadence 180 nm technology. The result shows that the power reduction is about 17% and a slight increase in area and delay of about 2% with respect to synchronous 3D NoC.

Delay Behaviour of Asynchronous Internet Router under Self-Similar Traffic Input-Queueing System with Markovian Input and Hyper-Erlang Services

Delay Behaviour of Asynchronous Internet Router under Self-Similar Traffic Input-Queueing System with Markovian Input and Hyper-Erlang Services

Artificial neural networks based dynamic priority arbitration for asynchronous flow control

Accesses to physical links in Networks-on-Chip need to be appropriately arbitrated to avoid collisions. In the case of asynchronous routers, this arbitration between various clients, carrying messages with different service levels, is managed by dedicated circuits called arbiters. The latter are accustomed to allocate the shared resource to each client in a round-robin fashion; however, they may be tuned to favor certain messages more frequently by means of various digital design techniques. In this work, we make use of artificial neural networks to propose a mechanism to dynamically compute priority for each message by defining a few constraints. Based on these constraints, we first build a mathematical model for the objective function, and propose two algorithms for vector selection and resource allocation to train the artificial neural networks. We carry out a detailed comparison between seven different learning algorithms, and observe their effectiveness in terms of prediction efficiency for the application of dynamic priority arbitration. The decision is based on input parameters: available tokens, service levels, and an active request from each client. The performance of the learning algorithms has been analyzed in terms of mean squared error, true acceptance rate, number of epochs and execution time, so as to ensure mutual exclusion.

AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip

Large scale synchronous network-on-chip (NoC) requires complex clock tree design, which leads to a large area overhead and power consumption. Based on handshaking protocols, asynchronous NoC does not have global clock tree distribution, which results in a natural power saving mode without any explicit clock gating. However, the faults occurring in such asynchronous networks will seriously affect their performances. In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed router is able to detect the faults of ports and links. Then, a fault-tolerant routing mechanism, based on the port priority in different quadrants, is proposed to maximize the number of packets that can be transmitted via the shortest paths. In this way, the fault-tolerance of asynchronous routers can be achieved. Besides that, AFTER could also achieve high scalability, and is suitable for the large scale globally asynchronous locally synchronous (GALS) system. The experimental results show that, when faults occur in the network, AFTER has a better fault-tolerance performance than the reference.

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result in a design in which data are transferred in a pipelined fashion, from the local memory of the sending core to the local memory of the receiving core, without any dynamic arbitration, buffering, and clock synchronization. The routers use two-phase bundled-data handshake latches based on the Mousetrap latch controller and are extended with a clock gating mechanism to reduce the energy consumption. The NIs integrate the direct memory access functionality and the TDM schedule, and use dual-ported local memories to avoid buffering, flow-control, and synchronization. To verify the design, we have implemented a 4 $\times $ 4 bitorus NoC in 65-nm CMOS technology and we present results on area, speed, and energy consumption for the router, NI, NoC, and postlayout.

Variation-aware approaches with power improvement in digital circuits

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.

Approximate Markovian model for delay behavior of internet router under self – similar traffic input

It has been reported that Internet Protocol (IP) packet traffic exhibits self-similarity or long range dependence (LRD) and causes degradation of router performance. Therefore, it is crucial for an appropriate buff er design of router. In this paper, we propose an approximate Markovian model for delay behavior of router under self-similar traffic input. Original 16 −MMPP which emulates the self-similar input traffic is approximated by 2 − MAP. Input traffic is assumed to be of asynchronous variable length. Numerical examples show that our method gives accurate results. This result can be applied in evaluating real time asynchronous router.

Asynchronous spatial division multiplexing router

Asynchronous quasi-delay-insensitive (QDI) NoCs have several advantages over their clocked counterparts. Virtual channel (VC) is the most utilized flow control method in asynchronous routers but spatial division multiplexing (SDM) achieves better throughput performance for best-effort traffic than VC. A novel asynchronous SDM router architecture is presented. Area and latency models are provided to analyse the network performance of all router architectures including wormhole, virtual channel and SDM. Performance comparisons have been made with different configurations of payload size, communication distance, buffer size, port bandwidth, network size and number of VCs/virtual circuits. Compared with VC, SDM achieves higher throughput with lower area overhead.

Communication modeling of multicast in all-port wormhole-routed NoCs

Multicast is one of the most frequently used collective communication operations in multi-core SoC platforms. Bus as the traditional interconnect architecture for SoC development has been highly efficient in delivering multicast messages. Since the bus is non-scalable, it can not address the bandwidth requirements of the large SoCs. The networks on-chip (NoCs) emerged as a scalable alternative to address the increasing communication demands of such systems. However, due to its hop-to-hop communication, the NoCs may not be able to deliver multicast operations as efficiently as buses do. Adopting multi-port routers has been an approach to improve the performance of the multicast operations in interconnection networks. This paper presents a novel analytical model to compute communication latency of the multicast operation in wormhole-routed interconnection networks employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.

QNoC asynchronous router

An asynchronous router for quality-of-service Networks on Chip (QNoC) is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each SL. VCs are assigned dynamically per packet in each router. The router employs fast arbitration schemes to minimize latency. Analytical expressions for a generic NoC router performance, area and power are derived, showing linear dependence on the number of buffers and flit width. The analytical results agree with QNoC router simulation results. The QNoC router architecture and specific asynchronous circuits are presented. When simulated on a 0.18 μm process, the router throughput ranges from 1.8 to 20 Gbps for flits 8–128 bits wide.

Asynchronous NoC Router Design

The Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents an asynchronous NoC router, for use in 2-D mesh-connected networks. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the messages priorities. The proposed router protocol and its asynchronous modeling are based on the Speed Independent State Transition Graph (STG) model. The generated STG are transformed into VHDL data flow descriptions and the low level implementation is based onto a parameterized library. This library integrates the popular asynchronous SI modules such as C-element, Q-element, fairly arbiter, etc. The device is implemented in 0.35 µm CMOS technology and its performance is compared with a synchronous router of the same functionality. The asynchronous router enables a higher data rate and a comparable silicon area.

Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine

The goal of this research is to enable the actual building of parallel machines. The example chosen in this paper is a heterogeneous parallel machine with an intrinsic asynchronous behavior. An asynchronous router fully supports such a logical asynchronism. However, every parallel processor would exhibit asynchronism similar enough to warrant the study of a general methodology. The main part of the paper deals with an original method that ensures a hazard-free self-timed design assuming the worst conditions for robustness. Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminated by an optimal covering. A new variable labelled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of the above-mentioned router. Peculiar fully customized cells were designed. Circuit-measured performances as well as some machine inner-communication performances are presented.