Asynchronous First In First Out Research Articles

A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO

In modern large scale ASIC designs, multiple clock systems are often involved, which can create problems with data transfer in different clock domains. A practical solution to this problem is the use of asynchronous FIFOs (First In First Out) for buffering the transfer of data from different clock domains. A high-capacity asynchronous FIFO cascaded with a synchronous FIFO is designed based on a conventional asynchronous FIFO using the Verilog language. The input data is processed across the clock domain by the asynchronous FIFO, and the data output from the asynchronous FIFO is cached and output again by the synchronous FIFO. The module increases the FIFO depth while enabling data to be transferred across the clock domain. The simulation is completed within the Modelsim software which accordingly verifies the two main roles of the FIFO in processing data, namely the cross-clock domain and the data caching function. Simulation results show that the asynchronous FIFO data is written and read correctly and that the empty/full flag signal is correct.

Bit-Width Conversion Based on Asynchronous FIFO

As digital integrated circuits become larger and larger, data transfer between different clocks and different bit widths becomes inevitable. For different clocks, asynchronous First In First Out (FIFO) can be used to solve very well. In this paper, we introduce the basic theory of asynchronous FIFO, and then implement the transfer between different bit widths based on asynchronous FIFO. By analyzing the bit-width conversion in two cases, input bit-width < output bit-width and input bit-width > output bit-width, we finally get a unified conversion idea: input data is assembled and input into asynchronous FIFO, and asynchronous FIF3O output data is split and output, and a bit-width conversion method is given by borrowing the storage function of asynchronous FIFO. Finally, the simulation is verified with the help of Verilog. By this method, an asynchronous FIFO can be implemented for conversion between various bit widths without considering the difference between input bit widths larger or smaller than output bit widths, and the conversion can be done in one step, thus improving the conversion efficiency.

Simulation and Implemetation of High-Speed Data Transmission Over Aurora Protocol Using FPGA

Abstract: This paper proposes a simulation and implementation of highspeed knowledge transmission over twin freelance aurora channels on One GTX (Gigabit Transceivers) twin TILE by configuring multi-gigabit transceivers (MGT’s), that area unit gift within the virtex-5 FPGA victimization aurora protocol. (Here GT suggests that Gigabit transceivers (GT) and X indicates that these transceivers belong to Virtex-5 FXT platform. FXT platform supports superior embedded systems with advanced serial connectivity). Firstly, a 128-bit parallel knowledge is to be generated victimization simulators, that area unit enforced victimization VHDL language. The asynchronous first-in first-out (AFIFO) takes this 128-bit knowledge as input and produces an output of 16-bit parallel knowledge. This knowledge goes to the aurora module in parallel type as serial frames (i.e., 8 frames, every frame consists of two bytes). Finally, the 128-bit parallel knowledge is transmitted to the receiver module serially over fibre optic cable at the speed of three.125Gbps victimization study options of virtex5 FPGA. to attain high speed, Multi-Gigabit Transceivers (MGT) area unit used. In virtex-5 FPGA, these Multi-Gigabit Transceivers area unit obtainable as arduous IPs that operates at the clock rate of 156.25 megahertz (MGT clock). For configuring these MGT’s, Aurora protocol is employed, that converts the parallel knowledge into serial knowledge and the other way around. Finally, the information is transmitted on 2 freelance aurora channels and any testing is distributed victimization chip scope professional analyser to verify the integrity of information. Keywords: Aurora protocol, Virtex-5 FPGA, MGT’s, AFIFO, twin freelance Aurora Channels, GTX twin TILE, Serial knowledge Transmission.

USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication

This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm 2 , respectively, at a supply voltage of 1.8 V and total pin number of 38.

Development and Implementation of Parallel to Serial data Transmitter Using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA

The objective of this paper is Development and Implementation of parallel to serial data converter using Aurora protocol for high speed serial data transmission at the rate of 3.125Gbps by using architectural features of Virtex-7 FPGA. It involves the study and configuring the Xilinx Core Generator Tool to achieve the required high speed serial data transmission by using of Aurora 8b/10b Protocol & Multi-Gigabit Transceivers present in Virtex-7 FPGA. Firstly, a 192-bit parallel data is generated using simulators, which is implemented using VHDL language. The 192-bit data is sent to Asynchronous First-In First-Out (AFIFO) as input and produces an output of 32-bit parallel data. This data is sent to the aurora module in parallel form as successive frames (i.e. 6 frames, each frame consists of 4 bytes). Finally, the 192-bit parallel data is transmitted to the receiver module serially over fiber optic cable at the rate of 3.125Gbps using architectural features of virtex7 FPGA. Finally, the data is transmitted on dual independent aurora channels and the entire logic will be tested for its complete functionality in standalone mode by porting on to the Virtex-7 FPGA based custom Hardware. Keywords: Aurora Protocol, Independent Aurora Channels, Serial Data Transmission, Virtex-7 FPGA, AFIFO, GTX TILE, MGT’s

Implementation of multichannel UART with FIFO

To meet modern complex control systems communication demands, the paper presents a multi-channel UART controller based on FIFO (First In First Out) technique. The paper presents design method of asynchronous FIFO and structure of the controller. This controller is designed with FIFO circuit block and UART (Universal Asynchronous Receiver Transmitter) circuit block to implement communication in modern complex control systems quickly and effectively. Form the communication sequence diagrams, it is easily to know that this controller can be used to implement communication when master equipment and slaver equipment are set at different Baud Rate. It also can be used to reduce synchronization error between sub-systems in a system with several sub-systems. The controller is reconfigurable and scalable

Design and verification of an efficient WISHBONE-based network interface for network on chip

In this paper, a generic asynchronous First In First Out (FIFO) based WISHBONE compatible plug and play Network Interface (NI) for Network on Chip (NoC) is designed and verified. Four different types of encoded asynchronous FIFOs namely binary, Gray, one-hot and Johnson are designed and analyzed. It is found that Gray-code asynchronous FIFO is the best to handle the asynchronous clock domain issues in NI. The control signals of the WISHBONE bus wrappers from/to asynchronous FIFOs and packing/unpacking modules are asserted concurrently at the same rising edge of the respective router and IP clocks to reduce the latency. The same NI has been utilized for transferring data between synchronous as well as asynchronous clock domains irrespective of clock frequency and phase differences. The proposed NI ensures the seamless high data throughput between the routers and IP cores with minimal latency, higher throughput, higher speed and utilized lesser area compared to the existing design.

Automated Verification and Clock Frequency Characteristics in CDC Solution

Recently, the design complexity of System-on-a-chip (SoC) has increased and additional functionalities have been added to SoC. Moreover, their operation clocks are frequently transferred from single clock domain to multiple clock domains. Because of the volume of the crossing signals and the variety methods of implementing crossed clock, the verification of clock domain crossings (CDCs) has become a very important and challenging task in deep submicron designs. Therefore, specialized CDC verification solutions can accurately detect CDC issues and efficiently debug the root causes of these problems that we require to perform design analyses. This paper describes certain case studies involving CDC verification and the relationship between clock and operating frequencies. Variable combination of clock frequencies rclk and wclk was evaluated for the asynchronous first-in first-out (FIFO) memory design. When a synchronizer was inserted, the power consumption decreased with the frequency; however, the performance achieved a dead point when wclk was about 1.3 times the value of rclk. The results confirmed that different combinations of clock frequency affected the circuit characteristics.

Multi-UART Controller with Programmable Modes of Operation

A Multi-UART controller is presented in this paper which will serve the purpose of communication between different systems or sub-systems of large system. The different systems or sub-systems of a large system will be able to operate at different baud rates and will use the UART (Universal Asynchronous Receiver Transmitter) to perform communication. This controller has different modes of operation—Normal, Bridge and Hub modes. The controller uses an asynchronous FIFO (First In First Out) block for communication purpose. This controller will reduce the synchronization errors between different systems or sub-systems which are communicating with each other. Since communication between sub-systems or different systems is handled by this controller it will not burden the master processor or main system with communication related operations. This paper improves over [2] as the modes of operation being incorporated in the design itself and are completely reconfigurable.

Low Latency High Throughout Circular Asynchronous FIFO

This paper describes a circular first in first out (FIFO) and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO's cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 μm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.

A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links

In this paper, a fast serial link, Serial Transparent Asynchronous First-in First-out Link (STAFF-Link), is introduced. Using such links, we construct a parallel processing system based on a workst...

Pausible clocking-based heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous and asynchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous first-in first-out (FIFO) channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshake signals to the local module clock is done in an unconventional way-the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshake signal satisfies setup and hold time constraints with respect to the local clock. In order to validate this scheme, we implemented a test chip in 0.5-/spl mu/m CMOS. This chip is designed as a ring, composed of two synchronous modules, an asynchronous module, and two asynchronous FIFOs. Each module functions as a receiver to one module and a sender to another module. Test results show that the chip functions reliably up to 456 MHz.