Asynchronous Elements Research Articles

An asynchronous parallel branch-and-bound algorithm

This paper presents a parallel branch-and-bound algorithm which is applicable to a loosely coupled multiprocessor with nonhierarchical interconnection network such as torus or hypercube. This algorithm is asynchronous and processing elements (PEs) start evaluation of nodes without being synchronized. Thus, when each PE finishes evaluation of one node, it can immediately start the evaluation of the next node. First, we compared the performance for parallel branch-and-bound algorithms which have almost the same communication overhead. From the simulation results it was confirmed that when the proposed algorithm is applied to a torus machine, an efficiency (speed-up rate divided by the number of PEs) is obtained which is about twice better than that of the existing synchronous algorithm for the improved tree machine and about 1.4 times better than that of the synchronous algorithm for a torus machine proposed by the authors. Interconnection networks among PEs suitable for parallelization of branch-and-bound algorithms were investigated by applying the algorithm in this paper to several kinds of interconnection networks among PEs. As the results, it was found that even in the case in which communication time between adjacent PEs has very little effect on the execution time of an algorithm, a hypercube machine realizes almost the same efficiency as that of an interconnection network with a larger degree of PEs.

Bipolar circuit elements providing self-completion-indication

An ordinary synchronous system uses clocks to determine data signal validity. To avoid the problems of distributing high-speed clocks and partitioning logic to fit within clock cycles, asynchronous circuit elements must provide their own completion indication using self-timing. Basic bipolar circuit elements which modify differential current-steering gate styles to achieve completion indication without increasing the number of wires between gate stages and with only about a 50% cost in transistor density per stage are proposed. >

Hazard-free design of mixed operating mode asynchronous sequential circuits

This paper presents a hazard-free design methodology for the design of asynchronous sequential circuits based on a combination of synchronous and asynchronous circuit elements. Earlier approaches to essential hazard-free design of asynchronous sequential circuits are based on any one of the two design philosophies: by the addition of delay elements to the state output, or by input gate modification. The former approach makes the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true. The design in this paper makes no assumption about the delays of the network and hence is applicable to any environment. In addition, the design in this paper uses the minimum number of self-synchronous transitions, thus making it faster than the earlier designs.

Pattern retrieval and learning in nets of asynchronous binary threshold elements

A training algorithm for network of asynchronous learning-threshold elements is presented and analyzed. The algorithm is based on the Hebbian hypothesis, and it allows adaptation of the learning-network parameters to changing pattern environments. In particular, the network's properties can be quantified in environments where pattern occurrence is random, with nonequal, nonstationary probability distributions. The state reassessment probabilities of neurons during information retrieval can also be nonstationary and not equal for all neurons. The trained network is a content-addressable memory. The authors evaluate its stabilization properties with respect to a given set of patterns, using the theory of Markov processes. The results are applicable for the determination of efficient coding for information that has to be stored, and for prediction of actual pattern-retrieval capabilities of the trained network. The authors include the popular sum-of-outer-products assignment as an analyzable specific case of their training procedure, and allow the steady-state analysis of a large group of sigmoidal learning curves. >

Design and implementation of tristables using c.m.o.s. integrated circuits

An implementation of ternary memory elements is presented. Different synchronous triflops are described and their experimental realisation is discussed. Also asynchronous memory elements based on the self-synchronisation of synchronous triflops are introduced. These triflops have been selected in order to have flexible ternary memory elements with simple excitation equations.