Asymmetrical DC Sources Research Articles

A new method for selecting optimum levels in asymmetric Cascaded H‐Bridge‐Multilevel Inveter with variable DC sources

SummaryIn general, cascaded H‐bridge multilevel inverters (CHB‐MLI) are typically operated with either symmetrical or asymmetrical input DC sources, set at predefined specific ratios such as binary (1:2) or trinary (1:3) in the case of asymmetry, to achieve the desired output voltage waveform. However, if any DC source fails to provide the predefined voltage magnitude, or CHB‐MLIs with unspecified DC source ratios are utilized, the output voltage waveform may exhibit unequal magnitudes between consecutive levels, thereby causing a significant increase in total harmonic distortion (THD). Conventionally, to mitigate this effect, the corresponding H‐bridge is bypassed through zero voltage switching, which leads to an additional burden on the remaining H‐bridges to serve the same load. To reduce the burden on the remaining cells and improve the THD profile of the inverter, this article proposes a novel method for CHB‐MLI with varying DC magnitudes. It aims to enhance the quality of the output voltage waveform by strategically selecting optimum voltage levels rather than utilizing all available levels when CHB‐MLI has unspecified or variable DC sources. This approach can achieve a more balanced distribution of voltage magnitudes across successive levels by eliminating redundant states. Moreover, the proposed technique can reduce switch losses and enhance the converter's efficiency. The proposed method is validated through MATLAB/Simulink software simulations, followed by experimental verification.

A dual source switched-capacitors multilevel inverter topology with extended voltage levels and voltage gain

The switched-capacitors multi-level inverters (SCMLI) are widely used in renewable energy resources for enhancing the quality and reliability of generated power. This paper suggests a new topology of extendable voltage levels and voltage gain units using switched capacitors SC with a dual DC source. The proposed unit can be extended by a modular pattern to increase the output voltage levels and voltage-boosting gain of the inverter. The main feature of this work is presenting a unit topology that utilizes multiple and modular sub-cells to increase the voltage gain at the output by increasing the number of the sub-cell components. A ternary relationship of the voltage magnitudes between the two asymmetrical DC sources is mandatory. Furthermore, all the capacitors are self-balanced, so there is no need for any additional and complex control circuit. Moreover, to decrease the cost factor of the inverter, a low IGBT switch count is taken into consideration and no passive diodes are used in the proposed structure. The H-bridge is connected to the unit to achieve bipolar voltage at the output. The operational analysis of the inverter is delineated in detail. A comparative study with state-of-art MLIs in different terms such as the number of components, the total standing voltage, the cost factor, and the gain shows the particularity of the proposed topology. The simulation of the proposed MLI is performed using PSCAD-EMTDC software. An experimental prototype is built to validate the simulation results.

Implementation of the Fuzzy Logic Controlled 31‐Level Diode Switched Multilevel Inverter with Optimal Components for Solar PV‐Fed System

This work presents a novel architecture for the 31‐level asymmetrical DC voltage source configured diode switched multilevel inverter, which has a single phase and fewer components. Using asymmetric DC sources and an H‐bridge, the proposed topology generates a maximum output voltage of 31 levels. This 31‐level topology is suitable for both renewable energy source conversion (RES) and electric vehicle (EV) applications. This topology requires fewer total components, lower cost, and smaller size. Along with the numerous benefits of MLIs, reliability issues are critical due to the larger number of devices required to minimize THD. Several characteristics, such as total standing voltage (TSV), reliability, cost function (CF), efficiency, and overall power losses, are investigated for the developed 31‐level MLIs. The TSV and CF of the proposed MLI are critical factors in demonstrating that the proposed topology is cost‐effective when compared to other recent topologies. Many parameters are thoroughly compared and tabulated, as well as represented graphically. The suggested MLI has lower TSV and component demand. Total harmonic distortion complies with IEEE specifications. The reliability aspects were also calculated and validated. The proposed MLI is controlled by a fuzzy logis controller (FLC) to achieve efficient results. The topology is simulated in MATLAB/Simulink software under a variety of conditions and dynamic load changes, and a prototype with a dSPACE controller is also implemented.

Solar PV-Fed Multilevel Inverter with Series Compensator for Power Quality Improvement in Grid Connected Systems

Power quality problems arise as a result of RES integration into the grid. Voltage fluctuations, harmonic distortion, and spikes all impact customers as power quality issues on the grid. A cheap series compensator, such as the Dynamic Voltage Restorer (DVR), is the best approach to fix these problems. In order to enhance the grid's power quality, this research introduces a novel multilayer inverter that uses solar PV as a distributed voltage rectifier. The main objective of the proposed work is to enhance power quality through the development of a DVR that simultaneously functions as an integrated 23-level multilevel inverter. Beyond that, the boost converter has an improved INC-MPPT implementation. Despite their numerous benefits, multilayer inverters encounter reliability concerns such as reduced total harmonic distortion (THD) and fewer components. The suggested design has the potential to produce 23 distinct output voltage levels by use of asymmetrical DC sources. An inverter that is both smaller and cheaper with fewer parts is one of the advantages of the MLI. On top of that, the dq reference frame rotation adjustment is well studied mathematically. To test the DVR's flexibility with an equal load, simulation approaches are used. The simulation results of the suggested structure are generated using MATLAB/Simulink. Results from the Fuzzy Logic System show that the proposed technique improves power quality and compensates better for voltage sag.

A Dual Source 13 Level Inverter with Reduced Component Count for Renewable Energy Applications

An innovative multilevel inverter (MLI) relying on switched capacitor (SC) architecture is suggested for single-phase inverters with 13-levels. This suggested SCMLI is expected to be capable of generating output AC voltages at appropriate levels while utilizing fewer switches. The suggested inverter utilizes two count of capacitors, two asymmetrical dc sources, two diodes, and 11 switches. As fewer switches are needed, fewer gate drivers are also needed, increasing the converter's power density. The challenge of preserving self-voltage balance across the capacitors in an SC-MLI circuit is yet another task. Additionally, when the modulation index is low, self-voltage preservation is subpar. It is possible to maintain the self-voltage balance with the capacitors connected in this suggested SC-MLI avoiding the requirement of any ancillary devices or challenging control schemes. Regardless of the modulation index values, capacitors operate at self-balanced levels in all regions of the spectrum. The suggested SC-MLI has a strong ability to achieve good power quality and can balance capacitor voltages even at low modulation indices. The suggested SC-MLI is first modelled using different loading conditions in the MATLAB/Simulink® platform, and subsequently it is validated with the help of typhoon-HIL real-time emulator. Using the simulation tool PLEXIM-PLECS, the suggested inverter's overall switching losses and efficiency are estimated and found out to be 95.87%.

The development of a generalized multilevel inverter for symmetrical and asymmetrical dc sources with a minimized ON state switch

This paper proposes a double source double diode double switch (DSDDDS) multilevel inverter to generate positive voltage and a connecting polarity changing circuit of an H-bridge inverter to generate negative voltage. By connecting the jth number of basic units in series, the desired level is obtained. Various algorithms, such as Natural, Binary, Trinary, and Quasi-Linear sequences, and two proposed algorithms are discussed to determine the magnitude of DC voltage sources in order to generate more stepped levels with fewer switches. The proposed multilevel inverter eliminates the need to turn on additional power switches for different levels, which is the main advantages of this topology. The proposed multilevel inverter is compared to conventional switched diode multilevel inverters in terms of switch count, number of ON state switches per level, driver circuits, and total standing voltage. Real-time results from the OPAL-RT test bench and simulation have validated the proposed inverter.

A New Design of Multilevel Inverter Based on T-type Symmetrical and Asymmetrical DC Sources

A New Design of Multilevel Inverter Based on T-type Symmetrical and Asymmetrical DC Sources

A novel multilevel inverter topology with reduced number of component count and total standing voltage for renewable energy conversion system

In this paper, a new Multi-Level Inverter is proposed for a renewable energy conversion system. It uses two asymmetrical DC sources in the ratio of 1:3. The Proposed topology generates N levels using N-16 DC sources, N+32 switches, and a self-balanced capacitor. In comparison to the existing topologies which use DC sources in the same ratio of 1:3, the proposed topology generates higher voltage levels with a reduced number of DC sources, switches, and minimum Total Standing Voltage (TSV). Further, the advantage of the proposed topology is that the voltage stress on each switch is less than or equal to the DC source voltage, which is not the case with existing topologies. The loss distribution at each switch is also found using PSIM software. This loss is around 10–15% of the total power losses in the converter. It shows an equal sharing of losses in each device. The proposed topology is simulated in MATLAB/SIMULINK. A Phase Disposition Level Shift PWM (PD-LSPWM) technique is used by considering the carrier frequency equal to the fundamental frequency (50 Hz). The experimental results are verified with a prototype model using dSPACE 1104 in the laboratory.

Reduced Voltage Stress Asymmetrical Multilevel Inverter With Optimal Components

The article presents a single phase asymmetrical multilevel inverter with a reduced components and low voltage stress which reduces the size and cost of the system. The structure provides a maximum output voltage of 23 levels with asymmetrical DC sources. There exists several reliability issues in lowering the total harmonic distortion (THD) by utilizing higher components in the design of MLI despite of its merits. Achieving reliability and lowering the THD is a challenging task for the researchers. The proposed 23-level MLI has been investigated with various performance parameters like total voltage standing (TSV), cost function (CF), power loss and efficiency analysis. The suggested MLI is compared with the existing topologies in the recent past and found that it has less voltage stress across the switches and cost-effective. The TSV calculations show that the proposed structure is more efficient in reducing the losses and increasing the efficiency. Hence, based on the evaluations and the comparisons made with the other topologies, it is found that the proposed MLI is well suited for the medium power applications such as FACTS, SVC, DSTATCOM and DVR. As the proposed architecture provides the 23 level output voltage values with asymmetrical DC sources, the configuration can be utilized for improving power quality in grid-connected renewable energy sources. The topology provides a less THD value which is under IEEE standards. The proposed architecture has been designed in MATLAB/Simulink and is implemented experimentally in hardware prototype in the laboratory environment.

Solar PV-Fed Multilevel Inverter With Series Compensator for Power Quality Improvement in Grid-Connected Systems

Power quality difficulties arise as a result of Renewable Energy Sources (RES) integrating with the grid. Voltage swell, sag, and harmonic distortion occur on the grid due to power quality issues, which have an impact on customers. An inexpensive series compensator, like the Dynamic Voltage Restorer (DVR), is the best solution for overcoming the aforementioned problems. In this article, a solar PV integrated DVR with a novel multilevel inverter is introduced to address the power quality issues in the grid. The main objective of the proposed work is to develop a DVR integrated with a 23-level multilevel inverter to enhance the power quality. In addition, an improved INC-MPPT technique is designed for the boost converter for maximum energy extraction from the solar PV modules. Despite numerous benefits of multilevel inverters, there exist several reliability challenges such as fewer component counts and reduced THD. The suggested topology can able to generate 23 levels of output voltage with asymmetrical DC sources. The MLI has several advantages such as a reduction in the overall component count, cost and size of the inverter. Additionally, a detailed mathematical analysis is presented for the rotating dq reference frame control. The dynamic performance of the DVR is evaluated with a balanced load and implemented experimentally. Simulation results of the proposed system are carried out using MATLAB/Simulink. The proposed system is implemented using a dSPACE controller with a laboratory hardware prototype and OPAL-RT real-time simulator setup as well. The results show that the design of the proposed system is more effective at compensating for voltage sag and improves the power quality significantly. The THD obtained at the grid side is lower, which is under IEEE standards.

A New Hybrid Cascaded Switched-Capacitor Reduced Switch Multilevel Inverter for Renewable Sources and Domestic Loads

This multilevel inverter type summarizes an output voltage of medium voltage based on a series connection of power cells employing standard configurations of low-voltage components. The main problems of cascaded switched-capacitor multilevel inverters (CSCMLIs) are the harmful reverse flowing current of inductive loads, the large number of switches, and the surge current of the capacitors. As the number of switches increases, the reliability of the inverter decreases. To address these issues, a new CSCMLI is proposed using two modules containing asymmetric DC sources to generate 13 levels. The main novelty of the proposed configuration is the reduction of the number of switches while increasing the maximum output voltage. Despite the many similarities, the presented topology differs from similar topologies. Compared to similar structures, the direction of some switches is reversed, leading to a change in the direction of current flow. By incorporating the lowest number of semiconductors, it was demonstrated that the proposed inverter has the lowest cost function among similar inverters. The role of switched-capacitor inrush current in the selection of switch, diode, and DC source for inverter operation in medium and high voltage applications is presented. The inverter performance to supply the inductive loads is clarified. Comparison of the simulation and experimental results validates the effectiveness of the proposed inverter topology, showing promising potentials in photovoltaic, buildings, and domestic applications. A video demonstrating the experimental test, and all manufacturing data are attached.

Selective Harmonic Elimination Based THD Minimization of a Symmetric 9-Level Inverter Using Ant Colony Optimization

This paper proposed a new topology of a symmetric single-phase multilevel inverter with the smaller number of semiconductor switches and optimized low-frequency control methods to optimize the Total Harmonic Distortion. A nine-level single phase output is obtained by eight number of active semiconductor switches, four diodes and four capacitors from two asymmetrical dc sources. The selected harmonic order in the output voltage is eliminated by the PWM (SHE-PWM) based on selective harmonic elimination. To optimize the switching angles, an ant colony optimization is introduced. The proposed SHE-PWM and ant optimization are implemented and tested for THD on the SIMULINK platform. The proposed approach offers less THD and is best suited to high-power applications with medium voltage.

Design and Implementation of 31-Level Asymmetrical Inverter With Reduced Components

This paper presents a novel topology for the single-phase 31-level asymmetrical multilevel inverter accomplished with reduced components count. The proposed topology generates maximum 31-level output voltage with asymmetric DC sources with an H-bridge. The fundamental 13-level multilevel inverter (MLI) topology is realized, and further, the topology is developed for 31-level can be used for renewable energy applications. This reduces the overall components count, cost and size of the system. Rather than the many advantages of MLIs, reliability issues play a significant role due to higher components count to reduce THD. This is a vital challenge for the researchers to increase the reliability with less THD. Several parameters are analyzed for both fundamental 13-level and developed 31-level MLIs such as total standing voltage (TSV), cost function (CF) and power loss. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with the cost function for the proposed MLI is compared with various topologies published recently and is cost-effective. A detailed comparison of several parameters with graphical representation is made. Less TSV and components requirement is observed for the proposed MLI. The obtained total harmonic distortion (THD) is under IEEE standards. The topology is simulated in MATLAB/Simulink and verified experimentally with a hardware prototype under various conditions.

A Novel Asymmetrical 21-Level Inverter for Solar PV Energy System With Reduced Switch Count

This article presents a novel asymmetrical 21-level multilevel inverter topology for solar PV application. The proposed topology achieves 21-level output voltage without H-bridge using asymmetric DC sources. This reduces the devices, cost and size. The PV standalone system needs a constant DC voltage magnitude from the solar panels, maximum power point tracking (MPPT) technique used for getting a stable output by using perturb and observe (P&O) algorithm. The PV voltage is boosted over the DC link voltage using a three-level DC-DC boost converter interfaced in between the solar panels and the inverter. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with a cost function for the proposed MLI is calculated and compared with multiple topologies published recently and found to be cost-effective. A detailed comparison is made in terms of switches count, and sources count, gate driver boards, the number of diodes and capacitor count and component count level factor with the same and other levels of multilevel inverter and found to be the proposed topology is helpful in terms of its less TSV value, devices count, efficient and cost-effective. In both simulation and experimental results, total harmonic distortion (THD) is observed to be the same and is lower than 5% which is under IEEE standards. A hardware prototype is implemented in the laboratory and verified experimentally under dynamic load variations, whereas the simulations are done in MATLAB/Simulink.

A Diamond Shaped Multilevel Inverter With Dual Mode of Operation

This study presents a novel multilevel inverter structure that can operate in both switched capacitor and asymmetric DC source modes. In the first mode, it can produce seven-level output voltage employing two switched capacitors and one single DC supply. The five-level output voltage is produced while operating the second mode. The voltage ratio between the input and output voltage for the capacitor mode is 1:3 (triple voltage gain). During the first mode, the capacitor of the inverter is self -balanced whereas the inverter can produce higher voltage output in the DC source mode. The proposed inverter reduces the total standing voltage in both modes of operations as it can generate the output voltage without requiring any additional H-bridge circuit. The feasibility and predominate features of the proposed inverter have been established by comparing with existing topologies in terms of power components count. Results obtained from this study are validated using simulation employing sinusoidal pulse width modulation (SPWM). A hardware prototype has also been developed for further validation.

Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

This paper introduces a modified multilevel inverter topology with asymmetrical dc sources combination. The significant features of the proposed circuit are the reduced number of switches and low total standing voltage (TSV). Proposed topology utilizes ten switches to produce 13 level output with per unit TSVp.u of 5.33. An additional feature of the proposed topology is the inherent negative level generation as there is no requirement of an H-bridge for the polarity reversals. Nearest level control (NLC) technique is used as the modulation strategy. Performance of the proposed topology is validated through extensive analysis using Simulink and PLECS software. Detailed circuit analysis and its power loss, as well as efficiency studies, have been carried out under constant and dynamic load conditions. Results obtained shows that the proposed topology is working well, producing an output of 13-level with total harmonic distortion of 6.36% and inverter efficiency of 98.8%. The topology is extended to n-level structure, and its generalized expressions for different parameters were formulated. The comparison of the generalized structure with other existing topology is carried out, and it is found that the proposed topology outperform other topologies on many parameters.

A Reduced Single-Phase Switched-Diode Cascaded Multilevel Inverter

The cascaded multilevel inverters (MLIs) are suitable topologies when a high number of voltage levels are needed. Nonetheless, cascaded topologies possess the main drawback of a high number of power switches and gate drivers that make sophisticated control, reducing efficiency, and increasing cost. This article proposes a new fundamental switched-diode topology that is capable of generating five positive-voltage levels with only three power switches, three power diodes, and three dc voltage sources. Based on a combination of the n number of new fundamental topology, two cascaded topologies are proposed, which increases the number of voltage levels and decreases the number of power switches and voltage stress. The proposed cascaded topologies can operate in asymmetric dc sources, so different dc voltage source magnitudes are submitted to minimize the number of components. The main advantages of the proposed cascaded topologies are reducing the number of power switches, and gate drivers with reasonable dc voltage sources count in comparison with other state-of-the-art cascaded topologies. Furthermore, the proposed topologies reduce the cost in comparison with other recent MLI topologies. The power loss analysis and the recommended application for the proposed topologies are discussed. The simulation and experimental works are presented to verify the operation correctness of the proposed topologies.

An Optimized Multilevel Inverter Topology with Symmetrical and Asymmetrical DC Sources for Sustainable Energy Applications

This paper proposes an optimized Multi-Level Inverter (MLI) topology with symmetrical and asymmetrical DC sources for sustainable energy applications. The proposed MLI has optimized components to reduce size, cost, and installation area in comparison with traditional MLIs. It also improves output power quality by reducing harmonics in the stepped output, and hence it can be used for sustainable energy applications with a grid interface. The proposed inverter is equipped with six switching devices, one clamping diode, and two DC sources. It produces a five-level stepped output when using symmetrical DC sources and a seven-level stepped output when using asymmetrical DC sources. In this topology, the six switching devices are divided into two units, namely the level generator and the polarity generator units, the switches used in the level generator are responsible for producing the required number of levels in the form of rectified stepped output and the switches used in the polarity generator are responsible for converting the rectified stepped waveform to stepped AC output. The simulation results verify the operation of the MLI when fed with linear load with symmetrical and asymmetrical DC sources, and the experimental output results are presented for validation.

A Step-Up Multilevel Inverter Topology Using Novel Switched Capacitor Converters With Reduced Components

In this article, basic cell (BC) of a novel switched capacitor converter (SCC) has been proposed first. After that, the generalized structure of proposed SCC is developed. The developed SCC requires reduced number of switches, drivers, diodes, capacitors, and lower number of conducting switches in current flow paths and capacitor charging paths as compared to the other recently developed SCCs. A switched capacitor multilevel inverter (SCMLI) utilizing two numbers of generalized SCCs is developed next. Further, cascaded extension of proposed SCMLI is realized and analyzed for symmetric and asymmetric dc source configurations. A detail analysis of optimum selection of capacitance for switched capacitors of 13-level SCMLI is presented. An extensive comparison study shows that the proposed SCMLI requires lower number of components as compared to other SCMLIs. Further, the proposed structure has minimum cost function per level per boosting factor as compared to the other SCMLIs. Extensive experimental results considering fundamental switching frequency scheme are presented to validate the merits and effectiveness of the proposed structure.

Cross-Switched Multilevel Inverter Using Novel Switched Capacitor Converters

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF /NL ) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure.