Asymmetric SRAM Research Articles

A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications

This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

Newly energy-efficient SRAM bit-cell using GAA CNT-GDI method with asymmetrical write and built-in read-assist schemes for QR code-based multimedia applications

The novel design of asymmetric single-ended ten-transistor SRAM bit-cell (SE 10T-SRAM) using gate-all-around (GAA) carbon nanotube (CNT) FETs-based GAA CNT-GDI method along with dual-chirality technique for CNTs, the asymmetric write-assist and built-in read-assist schemes in the presence of more saving area and less energy consumption is suggested for portable/mobile multimedia applications. Based on the analytical-compact model, an equation for calculating write-static margin (WSNM) is presented by expressing the degree of dependence of the metric on the power supply voltage variation for the suggested bit-cell structure. The results of extensive simulations to evaluate the proposed bit-cell in single and multi-array structures indicate better static/dynamic noise margins, less sensitivity to process, voltage and temperature (PVT) variations, improvement of basic parameters in the presence of contact length changes, more noise-immunity with scalability at cell supply voltage, and better results in other comprehensive figure of merits (FoMs) parameter compared to nanotechnology-based counterpart circuits with the same number of transistors in the 16 nm technology node. Also, evaluating the proposed structure in the presence of changes in the contact length parameter of other transistors as a contact length sizing-level solution, indicating the achievement of an improved structure in the basic parameters such as static noise margin, power consumption, and energy-delay product (EDP) parameter compared to the default structure with a minimum-sizing contact length. Finally, in order to use the proposed bit-cell in a real application, the suggested structure for storing images based on quick response (QR) code is examined with a link between MATLAB and synopsys H-SPICE simulator tools based on suggested algorithm. The results demonstrate that the suggested bit-cell is with more appropriate and significant results in terms of comprehensive FoMs, in which the evaluations concerning the appropriate accuracy in pixel-by-pixel storage of images based on the peak signal-to-noise ratio (PSNR) and the mean structural similarity index measure (MSSIM) metrics, compared to other well-known counterpart schemes confirms the superiority of the proposed design. Hence, the proposed design can be used for various areas regarding multimedia device applications.

Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

Reliable and high performance asymmetric FinFET SRAM cell using back-gate control

As the technology scales down, the performance characteristics are degraded and the reliability of digital circuits against soft error and aging effects are reduced. In this paper, we propose a reliable asymmetric FinFET 6T SRAM cell formed by the combination of tied-gate and independent-gate transistors. In the proposed design, we used a fixed value for the back gate voltages and utilized the back gate control method along with the built-in feedback. HSPICE simulations in 32 nm FinFET technology at VDD = 0.9 V indicate that the proposed cell has the highest read SNM, read speed, write stability, and the least read power consumption amongst recently reported cells. Furthermore, our proposed SRAM structure is the best soft error resilient design and, with a low difference, has the second least hold and read stability degradations against aging effect induced by negative bias temperature instability in comparison with other SRAM cells considered in this paper. In addition, the results demonstrate the efficiency of our proposed cell against process and environmental variations.

Highly robust asymmetrical 9T SRAM with trimode MTCOS technique

Memory design is the most complex part of any electronic devices. There are many parameters either intrinsic or extrinsic effects the system. In the memory design some features should be focus like stability, leakage current and delay. These parameters play important role in terms of performance. There is a lot of degradation in performance while not using the system. In this paper we used MTCMOS tech for optimizing parameters like stability static power dissipation and delay. We characterized the parameters of conventional 6T, Asym8T Asym 9T. The main focus is on the Asym 9T because it had low static power dissipation low delay and high stability. We simulated Asym 9T on different values of the threshold values and β values. Asym 9T SRAM cell exhibits high stability with dual threshold voltage.

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability

A novel six-transistor static random-access memory (6T SRAM) cell is proposed in this paper for enhancing the data stability and write ability as compared to the conventional memory circuits. Asymmetrically gate overlapped / underlapped FinFETs are employed as bitline access transistors in the proposed SRAM cell. The strength of the asymmetrical bitline access transistors are weakened during read operations. Furthermore, voltage transfer characteristics (VTCs) of cross-coupled inverters have narrower transition regions in the new SRAM cell as compared to the conventional SRAM cells. The proposed SRAM cell thereby provides stronger read data stability as compared to the conventional symmetrical SRAM cells. The strength of bitline access transistors are enhanced during write operations as the direction of current flow is reversed in the new asymmetrical SRAM cell. The power supply voltage of a selected word floats during write operations. The write voltage margin is thereby significantly increased with the proposed SRAM cell as compared to the conventional SRAM cells. The read data stability and write ability are both enhanced by up to 51.7% and 65.5%, respectively, with the proposed SRAM cell as compared to the conventional symmetrical six-FinFET SRAM cells in a 15[Formula: see text]nm FinFET technology.

A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to perform write operation without any write assist at VDD=1V. Monte Carlo simulations for an 8Kb SRAM (256×32) array indicate that the scalability of operating supply voltage of the proposed cell can be improved by 10% and 21% compared to asymmetric 5T- and standard 6T-SRAM cells; 21% and 53% lower leakage power consumption, respectively. The proposed 6T-SRAM cell design achieves 9% and 19% lower cell area overhead compared with asymmetric 5T- and standard 6T-SRAM cells, respectively. Considering the area overhead for the write assist, replica column and the replica column driver of 2.6%, the overall area reduction in die area is 6.3% and 16.3% as compared with array designs with asymmetric 5T- and standard 6T-SRAM cells.

Stable and Low Power 6T SRAM

In this paper an effort is made to design a stable and energy efficient asymmetrical 6T SRAM cell in 65nm technology generation with one bit line for read and one for write operation along with dual word lines. A simple energy recovery driver is added to enhance the write ability of the SRAM and to recover energy. Sizing the access transistor helps write ability and sizing of the pull down transistor provides better read stability. This circuit saves energy during write operation and also provides good read stability. General Terms Design, Experimentation, Performance

An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology

modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time.The design and simulation work for 6T-SRAM, NC-SRAM, Asymmetric SRAM, PP-SRAM, and P3-SRAM topologies have been carried out to see their power consumption and performance at 45nm CMOS technology at 300 o K for VDD=0.7V and 0.8V. At VDD=0.8V, P3-SRAM consumes 69.069%, 13.61%, 82.03% and 86.11% less standby power than 6T-SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively.Similarly, the dynamic power consumed by P3- SRAM is 88.88%, 89.23%, 85.25% and 89.5% less than 6T- SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively at VDD=0.8V.

Asymmetric Independent-Gate MOSFET SRAM for High Stability

In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array architecture is also suggested to prevent read stability degradation in the half-selected cell, where word line is selected but bit line is unselected. The previous SRAMs with IG-MOSFET (IG-SRAMs) fail to simultaneously improve read stability and writeability compared to the SRAM with the tied-gate MOSFET. The proposed IG-SRAM significantly improves both read stability and writeability at the cost of slightly increased bit-cell area and read delay, as compared to the previous IG-SRAMs.

Design of power-aware FPGA fabrics

We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

Most microprocessors employ the on-chip caches to bridge the performance gap between the processor and the main memory. However, the cache accesses usually contribute significantly to the total power consumption of the chip. Based on the observation that an overwhelming majority of the values written to the cache are 0, in this paper we propose a zero-aware SRAM cell with an asymmetric inverter pair, called ZA cell, to minimize the cache power consumption in writing 0. The ZA cell uses a circuit-level technique, which is software independent and orthogonal to other low-power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results based on the SPEC2000 and MediaBench traces show that without compromise of both performance and stability, the ZA cell can reduce the average cache write power consumption over 60% for both the baseline instruction and data caches. In particular, the ZA cell is attractive in the data caches, which reveal the high write-zero rate.