Asymmetric Source Configuration Research Articles

A nearest level control technique for an asymmetric source configuration of multi-level inverter topology

In this paper, an asymmetric source configuration of Multilevel Inverter (MLI) topology has been proposed. It consists of eight unidirectional switches, two bidirectional switches and four isolated DC sources. By considering 1:5 and 1:4 source configurations, the inverter produces 25-level and 21-level outputs respectively with the same switching action. For producing negative voltage levels, there is no requirement of separate backend H-bridge and inherently produces both positive and negative voltage levels. The main advantage of this topology is that in every state, only four switches are in ON mode and else are in OFF state. It also gives less per unit Total Standing Voltage (TSV) and thereby cost requirement of semiconductor devices can become decreases. For generating gate pulses, the simple Nearest Level Control (NLC) has been used by considering the round function. This technique is basically a fundamental switching frequency technique thereby switching losses are greatly reduces as compared with high switching frequency Pulse Width Modulation (PWM) techniques and it is particularly suitable for large number of levels. With this control technique, there is no inrush current has been developed at the input of DC sources. Finally, with step change in Modulation Index (MI) values the proposed topology with two different source configurations have been validated through MATLAB/Simulink platform.

A New Fault-Tolerant Multilevel Inverter Structure With Reduced Device Count and Low Total Standing Voltage

A new fault-tolerant (FT) multilevel inverter (MLI) structure that can tolerate the faults on the switches and sources is introduced in this article. The presence of redundant states in the proposed structure ensures the FT capability, which is an important requirement for emergency loads. Initially, the operation of the proposed FTMLI for fault-free and different fault conditions under symmetric and asymmetric source configurations is discussed. Furthermore, this article explores the ability of the proposed topology operating at different voltage levels in positive and negative half cycles of the output voltage to improve the reliability of the system. For this case, the modified pulsewidth modulation control strategy ensuring minimized lower order harmonics and zero dc offset is presented. The feasibility of the proposed topology is verified through simulation and experimental studies. Lower total standing voltage, reduced switch count, higher efficiency, and improved reliability are the key features of the proposed topology. A comprehensive evaluation and comparative study are performed to evaluate the performance of the proposed MLI over other structures.

DESIGN AND DEVELOPMENT OF 51 LEVEL NON MODULAR MULTILEVEL INVERTER TOPOLOGY WITH REDUCED NUMBER OF SWITCHES AND CONDUCTION PATH

In this paper, a 51 level multilevel inverter topology with non modular design is developed, which can be operated in asymmetrical mode with a reduced number of power switches and lesser conduction path. The proposed design has three separated DC sources and eleven active power switches, i.e., ten unidirectional switch and one bidirectional switch. The topology can be used with asymmetrical voltage source configuration to generate fifty one levels. This structure can be cascaded to produce maximum level by a series connection to produce higher voltage levels with less voltage stress on the switches without modifying the topology structure. A detailed Comparison is made with existing topology and recently introduced topologies based on the number of active switches, Separated DC sources, number of gate driver circuits. To prove the presented topology’s superiority, a simple Multicarrier pulse width modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through Matlab/Simulink simulation. KEYWORDS: Non Modular Multilevel Inverter, Reduced Switch.

DESIGN OF MODULAR AND NON MODULAR MULTILEVEL INVERTER TOPOLOGY WITH REDUCED NUMBER OF SWITCHES

In this paper, a new multilevel inverter topology with modular and non modular design is developed, which can be operated both symmetrical and asymmetrical mode with a reduced number of power switches. The proposed design has four separated DC sources and Nine active power switches. The topology can be used with symmetrical and asymmetrical voltage source configuration to generate seventeen and seven voltage levels. This structure can be cascaded to produce maximum level by a series connection to produce higher voltage levels with less voltage stress on the switches without modifying the topology structure. Comparison is made with existing topology and recently introduced topologies based on the number of active switches, Separated DC sources, number of gate driver circuits. To prove the presented topology’s superiority, a simple Multicarrier pulse width modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through Matlab/Simulink simulation. KEYWORDS : Modular, Non Modular Multilevel Inverter, Reduced Switch.

New Asymmetrical Modular Multilevel Inverter Topology With Reduced Number of Switches

In this article, a new single-phase multilevel inverter is introduced with a reduced number of power switches and reduced voltage stress on power switches. The proposed topology consists of four input dc sources and nine semiconductor switches (eight unidirectional and one bidirectional switch). The topology can be used for asymmetrical voltage source configuration to generate seventeen voltage levels. The extended topology is constructed by a series connection of the topology circuit to produce higher voltage levels with less voltage stress on the switches without modifying the existing structure. Comparison is made with traditional and recently introduced topologies based on the number of power switches, dc sources, total blocking voltage of switches, and gate driver circuits, to prove the proposed topology’s superiority. A simple nearest level modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through simulation and hardware experimental setup.

An Efficient Asymmetric Direct Current (DC) Source Configured Switched Capacitor Multi-level Inverter

This paper is dealing about Switched Capacitor Multi-Level Inverter (SCMLI) circuit which is controlled by triangular multicarrier Sinewave Pulse Width Modulation (SPWM) technique. The proposed SCMLI is powered from asymmetric DC source configuration to obtain multi-level output voltage by applying switching pulse to the main circuit from control circuit for switching operation. Fourteen switches and four capacitors are employing to do the proposed inversion operation in an effective way. Switching capacitors can perform boost operation to enhance voltage from the source level to the required level. Input DC from the asymmetric sources is converted to AC voltage for the application of consumers. This proposed conversion system is applicable for mainly in industrial and renewable energy-based energy conversion system because it can carry high output voltages. This proposed method gives about more efficiency. Also reduces switching losses in lower value, low conduction losses and capacitor ripple losses. The simulation model is analyzed in MATLAB/SIMULINK platform and the same validated in hardware results. The developed SCMLI structure is witness over other topologies for the power inversion process in the multi-level.

Multilevel inverter with improved basic unit structure for symmetric and asymmetric source configuration

An improved multilevel inverter (MLI) topology using a new basic unit structure with a reduced number of components is proposed in this study. Its single compact module is made up of two basic units connected to the left and right sides of a packed H-bridge. The topology produces 9-Level output when operated symmetrically and 17-Level output when operated asymmetrically. Identical magnitude of DC sources is used for the symmetrical operation, while non-identical magnitudes in a trinary sequence are used for the asymmetrical operation. The low-frequency modulation scheme is applied for the switching control where the switching angles are pre-calculated. The mathematical formulations for the switching are also considered to reduce the total harmonic distortion (THD) at the output. The proposed topology is also found to be superior in terms of the required number of switches per output level and total blocking voltage compared to conventional and recently reported MLIs. With these merits, real-time installation of the proposed topology will potentially require lesser space and become cheaper. The feasibility of the proposed topology is validated for its 9-Level and 17-Level operations through experimental verification on output characteristics, THD, blocking voltage, power-sharing and efficiency.

A Step-Up Multilevel Inverter Topology Using Novel Switched Capacitor Converters With Reduced Components

In this article, basic cell (BC) of a novel switched capacitor converter (SCC) has been proposed first. After that, the generalized structure of proposed SCC is developed. The developed SCC requires reduced number of switches, drivers, diodes, capacitors, and lower number of conducting switches in current flow paths and capacitor charging paths as compared to the other recently developed SCCs. A switched capacitor multilevel inverter (SCMLI) utilizing two numbers of generalized SCCs is developed next. Further, cascaded extension of proposed SCMLI is realized and analyzed for symmetric and asymmetric dc source configurations. A detail analysis of optimum selection of capacitance for switched capacitors of 13-level SCMLI is presented. An extensive comparison study shows that the proposed SCMLI requires lower number of components as compared to other SCMLIs. Further, the proposed structure has minimum cost function per level per boosting factor as compared to the other SCMLIs. Extensive experimental results considering fundamental switching frequency scheme are presented to validate the merits and effectiveness of the proposed structure.

Cross-Switched Multilevel Inverter Using Novel Switched Capacitor Converters

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF /NL ) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure.

Reduced device count version of single‐stage switched‐capacitor module for cascaded multilevel inverters

Switched capacitors are being increasingly employed in multilevel inverters for various applications. Of the new topologies that have been recently introduced, single-stage switched-capacitor module (S 3 CM) has gained a lot of attention. In this work, a modified version of S 3 CM is presented that leads to a significant reduction in a number of power switches, with a simultaneous reduction in total peak inverse voltage. The proposed topology can generate 9 voltage levels in symmetric configuration and 11 voltage levels in asymmetric configuration with two dc sources, two capacitors, and eight power switches. Moreover, for the higher voltage-rated power switches in the structure, the switching losses are minimised by fundamental frequency operation of these switches. The operation and the performance of the proposed topology have been validated through simulation and experimental results of a single-phase prototype with symmetric and asymmetric source configurations.

Reduction in components using modified topology for asymmetrical multilevel inverter

PurposeThis study aims to propose a modified topology for an asymmetric multilevel inverter as a basic module that generates 13-level output voltage waveform. The basic module consists of eight switches (unidirectional and bidirectional switch) and four DC voltage sources with unequal magnitudes. The proposed topology reduces the number of switches, isolated DC sources, cost and size of the circuit significantly as compared to other topologies. In addition, the proposed circuit provides a modular structure for a multilevel inverter.Design/methodology/approachThe proposed configuration is implemented through simulation and hardware development of a single-phase 13-level inverter prototype. A multicarrier-based pulse width modulation scheme is adopted for generating switching signals by using dSPACE real-time controller.FindingsTo demonstrate the advantages of the proposed configuration, a comparative analysis is carried out with other multilevel topologies in terms of number of switches, gate driver circuits, on-state switches and blocking voltage on the switches. The comparison results confirmed that the proposed configuration requires less number of components for the same number of voltage levels. Moreover, the peak inverse voltage on switches and losses is lower in the proposed configuration.Originality/valueIn the available literature, numerous topologies are presented with main emphasis on the reduced components count. In this study, the authors proposed a new topology for an asymmetrical source configuration. The performance of the proposed topology under steady-state and dynamic conditions is evaluated using simulation and experimental implementation.

Step-up Switched Capacitor Multilevel Inverter with a Cascaded Structure in Asymmetric DC Source Configuration

Step-up Switched Capacitor Multilevel Inverter with a Cascaded Structure in Asymmetric DC Source Configuration

Investigation of single phase reduced switch count asymmetric multilevel inverter using advanced pulse width modulation technique

In this paper, a new topology for Multilevel Inverter (MLI) with reduced switch count is proposed with an asymmetric dc source configuration. This configuration is used to double the output voltage level in multilevel inverter based on switched dc sources, by adding two switches with dc sources. The increased number of levels in the output voltage reduces the filtering requirements. The working principle of the proposed asymmetric inverter is presented through the single phase fifteen level inverter. The harmonic contents of different modulation indices are examined. The performance analysis of the inverter is compared with trapezoidal and Sinusoidal Pulse Width Modulation (SPWM) in terms of Total Harmonic Distortion (THD), fundamental rms voltage (V rms ) and Crest Factor (CF). The simulation results for the same are evaluated using MATLAB/SIMULINK

Comprehensive review of a recently proposed multilevel inverter

As multilevel inverters are gaining increasing importance, newer topologies are being proposed to reduce part count for large number of levels in output voltage. A simplified five-level inverter has been recently reported in the literature to reduce component count. The topology comprises of floating input DC sources connected in opposite polarities through power switches. The structure requires lesser active switches as compared with conventional cascaded H-bridge topology with much reduced switching losses. Available literature present generalisation of the topology with symmetrical sources, but no investigations are made for equal load sharing and asymmetrical configurations. This study presents a comprehensive analysis of the aforementioned topology, referred to as cross-connected sources-based multilevel inverter (CCS-MLI). The topology is analysed for both symmetric and asymmetric source configurations. Also, a new algorithm for asymmetric source configuration suitable for CCS-MLI is proposed. A control scheme is also proposed for equal load sharing in five-level topology. Investigations are made for possibility of equal load sharing in higher level structures and fundamental frequency switching of switches bearing higher voltage stresses. Various concepts are verified with simulations and experimental studies.

Topology for multilevel inverters to attain maximum number of levels from given DC sources

This study introduces a new multilevel converter topology, which can synthesise all possible additive and subtractive combinations of input DC levels in the output voltage waveform with fewer power electronic switches. An appropriate modulation scheme has also been proposed for low switching frequency operation of the proposed topology. As compared with the classic multilevel topologies, the proposed topology results in reduction of the number of switches and conduction losses. The operation and performance of the proposed multilevel converter has been ascertained through simulations and verified experimentally for single-phase nine-level multilevel inverter. Moreover, a 15-level inverter with asymmetric source configuration has been also investigated for charge balance control using the proposed modulation scheme. The same has been verified experimentally for effective balanced power delivery.