Asymmetric Doherty Power Amplifier Research Articles

Bandwidth Extension of the Doherty Power Amplifier Using the Impedance Distribution and Control Circuit for the Post-Matching Network

Owing to the high impedance transformation ratio, the Doherty power amplifier (DPA) with a large output power back-off generally has bandwidth limitations. This study proposes an asymmetric DPA with an impedance distribution and control circuit (IDCC) at the post-matching network to improve the bandwidth. The IDCC, based on a resonance circuit and a series transmission line, distributes and controls the load impedance according to the frequency so that the bandwidth of the DPA can be extended. To verify the proposed IDCC, an asymmetric DPA was designed using GaN HEMT with a power capacity of 6 W and 10 W for the carrier and peaking amplifiers, respectively. The implemented DPA was evaluated for the broad frequency band between 3.3 GHz and 3.8 GHz using a 5G new radio (NR) signal with a bandwidth of 100 MHz and a peak-to-average power ratio of 7.8 dB. A drain efficiency between 43.2% and 50.7% and an adjacent channel leakage power ratio between –23.4 dBc and –27.3 dBc were achieved at an average power level that ranged between 33.5 dBm and 34.3 dBm.

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Continuous Class-J/F-1 Mode Asymmetrical Doherty Power Amplifier With Extended Bandwidth and Enhanced Efficiency

This article presents a design method of continuous class-J/F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> mode asymmetrical Doherty power amplifier (DPA) using the phase tuning technique. By properly adjusting the phase characteristics of the output matching network (OMN) of the carrier amplifier (CA) and the harmonic impedances of the postmatching network (PMN), the load impedance of CA can be effectively tuned to meet the impedance requirements of continuous class-J and continuous class-F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> modes at the power back-off point, which thus extends the bandwidth with enhanced power back-off efficiency. In addition, the proposed DPA can theoretically achieve saturation efficiency of more than 58.7% over the working frequency. Based on the proposed method, a broadband continuous class-J/F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> mode asymmetrical DPA operating from 1.3 to 2.5 GHz (63%) is designed and measured. Under the continuous wave stimulation, the measured 9-dB back-off, 6-dB back-off, and saturation efficiencies are 55%–62.5%, 52.4%–65.6%, and 62.5%–81%, respectively. The measured 9-dB back-off and saturation gains are 8.8–11.3 and 7–10.6 dB, respectively. When driven by a 20-MHz long-term evolution (LTE) modulated signal with 9.9-dB peak-to-average power ratio (PAPR), the measured average efficiency is 47%–59% and the adjacent channel power ratio is from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 23.6 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 31.7 dBc.

A Broadband Asymmetrical Doherty Power Amplifier With Optimized Continuous Mode Harmonic Impedances

A Broadband Asymmetrical Doherty Power Amplifier With Optimized Continuous Mode Harmonic Impedances

Broadband Asymmetric GaAs MMIC Doherty Power Amplifiers With Simplified Peaking Matching Network and Output Capacitance Compensation

This letter proposes a compact asymmetric Doherty power amplifier (DPA) structure with a simplified peaking matching network (MN), and the output capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm{OUT}})$</tex-math> </inline-formula> of the peaking transistor is considered under different power states. The load–pull, including the MNs of carrier and peaking branch, is taken place to demonstrate the suggested scheme. For verification, a monolithic microwave integrated circuit (MMIC) DPA was designed and manufactured using a 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m GaAs process. The measurement results show that over a wideband of 4.3–6.0 GHz, the saturated output power is 29.4–30.4 dBm with a drain efficiency (DE) of 46.4%–57.1%. At 9-dB power back-off (PBO), the DE is 31%–43%.

Compact Asymmetrical Quasi-MMIC Doherty Power Amplifier

This paper presents a compact asymmetrical Doherty power amplifier (PA) based on a quasi-MMIC configuration for 5G sub-6 GHz applications. The proposed Doherty PA is composed of commercial GaN HEMTs and several passive components implemented on a silicon (Si) substrate. In order to achieve size and cost advantages, passive components such as a power divider, input matching networks, output matching networks, and a Doherty combiner are realized using Si-integrated passive device (Si-IPD) technology, which costs about 40% of the budget for the entire GaN MMIC process. For the 3.5 GHz pulsed-continuous waveform signal, the fabricated Doherty PA has an efficiency of 52.6% at a saturated output power of 44.2 dBm. Furthermore, an efficiency of 45.6% was achieved with the output power back-off (OBO) of 7.0 dB. The implemented PA occupies only 8.9 mm × 5.6 mm.

A C-Band Broadband Asymmetric Doherty Power Amplifier Using Phase Compensation and Low Q Technology

In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25[Formula: see text][Formula: see text]m gallium-nitride (GaN) process with a compact chip size of 2.9 mm × 1.9 mm in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5 dBm with 800 MHz bandwidth from 6.6 to 7.4 GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power.

A novel compact asymmetric Doherty PA design using symmetric transistors

AbstractA novel 7.2 dB output power back off Doherty power amplifier (DPA) based on asymmetrical load is proposed using two same transistors in this paper. To get maximum efficiency at back‐off output power and the largest saturate output power level simultaneously, the carrier power amplifier (PA) is matched to the maximum efficiency region when peaking PA is almost off, and both of the two PAs are matched to maximum power region to get largest output power. According to the proposed design methodology, high efficiency at back‐off power and high peak power DPA is designed and fabricated with two Cree's GaN HEMT CGH40010F devices. Measurements results show that the saturated output power of the DPA is over 44.5 dBm, the drain efficiency when 7.2 dB output power back off and saturate power are above 42% and 53%, respectively, in the range of 3.4–3.8 GHz. Meanwhile, better than −47.8 dBc adjacent channel leak power ratio can be achieved with digital predistortion under 20 MHz LTE signal testing at 3.4 GHz, the final design size is only 14 × 12 cm2.

A 9 dB back‐off dual‐band asymmetric Doherty power amplifier using dual peaking amplifiers for reactance compensation

AbstractThis paper proposes a dual‐band asymmetric Doherty power amplifier (ADPA) with 9 dB power back‐off range using dual parallel peaking amplifiers to realize reactance compensation for wideband operation at two frequency bands. To achieve dual‐band amplification, the specific phase delays of the carrier and peaking output matching networks (OMNs) required on the two target frequency bands were determined using the phase delay period repeatability principle combined with the Doherty impedance transformation first. Then, the carrier and peaking OMNs were designed according to the desired phase delay. More specifically, two parallel peaking amplifiers using the low‐order impedance transformation network were combined to generate the desired compensating reactance at the back‐off power range for wideband operation. For verification, a dual‐band ADPA operating over 2.35–2.75 and 3.2–3.6 GHz frequency bands was designed and measured. Experimental results show that, for the two frequency bands, the efficiencies at saturation are 53.6%–64.3% and 48%–67.8%, with the 9 dB back‐off efficiencies reaching 41.5%–53.3% and 40.5%–52.8%, respectively. When stimulated by a 20 MHz modulated signal, the designed ADPA can achieve the adjacent channel leakage ratio of −48 dBc after linearization.

A 37-GHz Asymmetric Doherty Power Amplifier With 28-dBm P sat and 32% Back-Off PAE in 0.1-μm GaAs Process

In this article, the analysis, design, and development of a 37-GHz asymmetric Doherty power amplifier (DPA) are presented. In a practical DPA, the main power amplifier (PA) shows nonideal characteristic, which varies the effect of the load modulation. Based on the theoretical analysis, we derive the relationship among the efficiency, power back-off (PBO) level, and the corresponding load impedance in a nonideal load modulation. The result suggests that a Class-AB main PA shows a decreased PBO efficiency during the load modulation. To achieve a good compromise between PBO level and PBO efficiency of the main PA, the load modulation scheme is redesigned in this work. A 2-dB PBO of the main PA is chosen to maintain the high efficiency during the load modulation. An asymmetric DPA topology is employed to compensate the inadequate PBO of the main PA so that a desired 6-dB PBO is achieved. Generally, the RF leakage at the DPA output degrades its performance. To solve this issue, we propose a modified low characteristic impedance DPA output network. The output matching network of the auxiliary PA is particularly designed to enlarge its output impedance. Through these design techniques, the leakage loss is significantly reduced to 0.2 dB, which improves the gain and power-added efficiency (PAE) at PBO. To validate the proposed techniques, a DPA chip is designed and fabricated in a D-mode 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. At 37 GHz, the 1.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm integrated chip exhibits a measured small-signal gain of 15.6 dB and a saturated power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$ </tex-math></inline-formula> ) of 28.0 dBm, with an associated 33.2% peak PAE and a 32.0% PAE at 6-dB PBO. To the best of our knowledge, the proposed chip exhibits the state-of-the-art overall performance among DPAs operating around 37 GHz for 5G n260 millimeter-wave (mm-wave) band.

A Time-Domain Multi-Tone Distortion Model for Effective Design of High Power Amplifiers

This paper proposes a new time-domain multi-tone distortion (TD-MTD) model suitable for accurately predicting the non-linear behavior of packaged high power radio frequency (RF) transistors over a range of discrete non-uniformly distributed frequencies. This proposed TD-MTD model uses a single expression rather than multiple distinct frequency specific behavioral models to describe the underlying behavior of the high power RF transistor at multiple fundamental frequencies. Furthermore its extraction is carried out using a time-domain representation of the travelling waves that can be acquired using a generic vector load-pull characterization system and without imposing additional requirements. The proposed model is extracted as an artificial neural network (ANN) and is implemented as a Netlist to serve in a harmonic balance simulator based power amplifier design process. The proposed model is validated in two phases. First, its ability to reproduce the large-signal behavior of a high power RF LDMOS transistor was demonstrated in simulation. Then, the TD-MTD model was used to validate the design of a high power two-way asymmetric Doherty power amplifier and the simulated output-power-dependent power efficiency, AM/AM, AM/PM and input return loss characteristics were compared to those obtained in measurement. The excellent agreement between the simulation and measurement results confirms the usefulness of the proposed model despite the simplicity of its extraction routine and measurement data.

A Broadband Asymmetric Doherty Power Amplifier Design Based on Multiobjective Bayesian Optimization: Theoretical and Experimental Validation

In this paper, a new multi-objective Bayesian optimization (BO) algorithm is applied to design a broadband gallium nitride (GaN) based Doherty power amplifier (DPA). The optimization process can be automatically implemented by combing the proposed methodology with a commercial simulation software. The performance of the DPA optimized by the proposed method is compared with those obtained with the initial designed DPA, the DPA optimized by existing BO method, and DPA optimized by the optimizers built-in using the commercial software advanced design system (ADS). The comparison results reveal that the DPA designed with the proposed method can achieve better performance with less optimization time than other optimization methods. The measured results show that the optimized DPA with the proposed method achieves a 9-dB back-off efficiency of 44.6%-65% and a saturated efficiency of 60.5%-78% from 2.0 GHz to 2.6 GHz, with saturated output power varying from 43.8 dBm to 45.2 dBm.

Frequency analysis of load modulation networks for asymmetric Doherty power amplifiers in GaN

AbstractThis paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.

Asymmetric Doherty Power Amplifier with Input Phase/Power Adjustment and Envelope Tracking

In this paper, the design and implementation of a Doherty power amplifier (DPA) are proposed using gallium nitride high electron mobility transistors (GaN HEMTs). Class-F and Class-C modes are combined to obtain an asymmetric DPA. The precise active load-pull controlling of fundamental and harmonic terminations of the DPA is simulated and analyzed, including the parasitics of the transistors. The measurements of the DPA with the phase difference, input power ratio adjustment, and envelope tracking of the auxiliary PA are discussed in detail in order to achieve a competitive performance. A greater than 63% drain efficiency is obtained within the 10-dB input power dynamic range at 2.1 GHz. The peak of the drain efficiency reaches 73%, with a corresponding output power of 46 dBm.

High efficiency Doherty power amplifiers for modern wireless communication systems: A brief review

Due&lt;span lang="EN-MY"&gt;to the high peak to average power ratio (PAPR) of modern modulated signals, power amplifiers (PAs) have been forced to operate at the back-off (BO) region of their saturation power in order to avoid signal clipping and distortion. However, classical PAs suffer from low efficiency in the BO region operation. Therefore, efficiency has to be enhanced in that region. Many techniques have been proposed. Among them, the Doherty power amplifier (DPA) is considered as the most suitable technique due to its simple structure and high performance. However, its conventional design is limited to a 6 dB BO level, which does not satisfy the requirements of modern communication systems. In this paper, a brief review of the most significant techniques of high-efficiency DPA is presented. First, DPA topology and its operation principles are briefly discussed. Second, efficiency enhancement techniques such as an asymmetrical DPA, output combiner modification, gate bias adaption, offset line optimization, and multi-way DPA were discussed. The study shows that the most suitable, simple, and effective solution is an asymmetrical approach. However, it needs to be investigated in terms of bandwidth in order to meet the efficiency-bandwidth requirements of modern wireless communication systems such as &lt;/span&gt;5G.

복소결합부하를 이용한 3.5 GHz 대역의 고효율 비대칭 도허티 전력증폭기 설계

In this study, a high-efficiency asymmetric Doherty power amplifier (DPA) based on a complex combining load (CCL) is presented. The CCL method extends the range of output back-off (OBO). This article provides a graphical design method using the Smith chart for the CCL-DPA load network. The proposed asymmetric DPA is designed using 6 and 10 W GaN-HEMTs for carrier and peaking amplifiers, respectively. With 3.5～3.6 GHz continuous-wave signal excitations, the implemented asymmetric CCL DPA exhibits a DE of 60.0～64.7 % and a PAE of 54.8～59.9 % at a maximum output power of 42.0～43.0 dBm. In addition, it has a DE of 51.3～51.6 %, and a PAE of 46.7～47.6 % at an output power of 35.0 dBm. Using an LTE signal with a PAPR of 7.5 dB and a signal bandwidth of 20 MHz, a power gain of 10.7～11.5 dB, a PAE of 44.0～45.1 %, a DE of 48.1～48.5 %, and an ACLR of −31.1 dBc are achieved. Using DPD linearization, ACLR is improved to −49.3/−50.4 dBc at an average power of 35.0 dBm.

2.6-GHz Integrated LDMOS Doherty Power Amplifier for 5G Basestation Applications

This letter presents a compact output combining network for a packaged integrated asymmetric Doherty power amplifier (DPA) by taking advantage of device drain source capacitance, Cds and package parasitic components. A new method is introduced to/of/for absorbing part of the peaking amplifier's C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> into the impedance transformer, thus extending the C- L- C-based “ C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> -absorption” technique to two-way asymmetric DPAs. Based on the proposed combining network, a two-stage laterally-diffused metal-oxide semiconductor (LDMOS) integrated asymmetric DPA was designed and fabricated at 2.6 GHz. The fabricated RF integrated circuit (RFIC) is mounted in a quad flat no-lead (QFN) package. Under a single-tone continuous-wave (CW) signal at 2.6 GHz, the DPA achieves a peak power of 46 dBm, a linear gain of 31.7 dB, and a 48% power-added efficiency (PAE) at 8-dB output power back-off (OBO). The DPA also demonstrates good linearizability by meeting the 5G spectrum mask and achieving a digital predistortion (DPD) corrected adjacent channel power ratio (ACPR) better than -51.5 dBc for 160-MHz long-term evolution (LTE).

Enhancing Bandwidth and Back-Off Range of Doherty Power Amplifier With Modified Load Modulation Network

This article presents a novel methodology for designing a broadband Doherty power amplifier (DPA) with extended output power back-off (OBO) range. A modified load modulation network (LMN) is proposed to enhance the OBO range and the bandwidth of the DPA simultaneously. Analysis is conducted to explore the relationship between the proposed LMN parameters and the broadband performance under various OBO levels. Generalized design formulas of the LMN parameters are then introduced to offer the broadband solution for arbitrary current ratios and OBO levels. An asymmetric DPA is demonstrated and implemented with gallium nitride (GaN) transistors using the proposed approach. The fabricated DPA operates from 1.4 to 2.5 GHz with 9-dB OBO range. The measured drain efficiency reaches 61%-75.5% at saturation and 44.6%-54.6% at 9-dB OBO within the operating bandwidth. When driven by a 60-MHz modulated signal with 9-dB peak-to-average power ratio (PAPR), the fabricated DPA attains 47.4%-53.5% average drain efficiency and better than -45.5-dBc adjacent channel leakage ratio (ACLR) after digital predistortion.

Doherty Power Amplifier for LTE-Advanced Systems

The design and implementation of an asymmetrical Doherty power amplifier are discussed, where two Cree GaN High Electron Mobility Transistors (HEMTs) devices are used for designing an asymmetrical Doherty power amplifier to achieve saturated power of 48 dBm and optimal back-off efficiency of 8 dB in the frequency band of 3.3–3.5 GHz. Rogers RO4350B material is used as a substrate material, a back-off of 8 dB was achieved with an average gain of 10 dB. Load-pull data are an important tool for determining the optimum load impedance that the transistor needs to see. Additionally, the measured efficiency was 50% when the designed amplifier was tested by a modulated signal of 8 dB peak-to-average-power ratio when the average output power was 40 dBm. At the same time, the linearity of the designed amplifier was measured and found 31.8 dB which can be improved using a digital pre-distorter. The gain phase measurement can be used as an indicator for compensating the phase difference between the two cells.

Harmonic‐tuned continuum mode active load modulation output combiner for the design of broadband asymmetric Doherty power amplifiers

The conventional Doherty output combiner limits the bandwidth of operation in the asymmetric Doherty power amplifiers (DPAs). In this study, an output combiner that is designed using a harmonic-tuned continuum mode active load modulation technique is proposed with the main target of extending the bandwidth of operation in the asymmetric DPAs. Through this methodology, design equations are derived and multiple harmonic impedance solutions are provided. This offers greater freedom for designing the output combiner of the asymmetric DPA which consists of the impedance inverting network and the impedance transforming network. Moreover, enhancements in the efficiencies at back-off and saturation power levels are made possible. The efficacy of the design strategy is demonstrated by the realised broadband asymmetric DPA prototype working within the band of 1.4–2.45 GHz. The experimental results have shown 54.55% bandwidth of operation, accounting for about 0.95–12.55% increment in bandwidth as compared with some recently published DPAs in the literature. Substantially, drain efficiencies within 35.5–52% at 6 dB output power back-off level and 47.5–64.2% at peaking power level are also recorded from the experiments. The maximum output power and gain are recorded at 43.52 dBm and 13.03 dB, respectively.