Associative Parallel Processor Research Articles

GIRAF: General Purpose In-Storage Resistive Associative Framework

GIRAF is a General purpose In-storage Resistive Associative Framework based on resistive content addressable memory (RCAM), which functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing deep in-data, rather than near-data, processing. We show that GIRAF outperformed a reference computer architecture with a bandwidth-limited external storage access on a variety of data-intensive workloads. The performance of GIRAF Dot Product and Sparse Matrix-Vector multiplication exceeds the attainable performance of a reference architecture by 1200 × and 130 ×, respectively.

PRINS: Processing-in-Storage Acceleration of Machine Learning

Machine learning algorithms have become a major tool in various applications. The high-performance requirements on large-scale datasets pose a challenge for traditional von Neumann architectures. We present two machine learning implementations and evaluations on PRINS, a novel processing-in-storage system based on resistive content addressable memory (ReCAM). PRINS functions simultaneously as a storage and a massively parallel associative processor. PRINS processing-in-storage resolves the bandwidth wall faced by near-data von Neumann architectures, such as three-dimensional DRAM and CPU stack or SSD with embedded CPU, by keeping the computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that PRINS-based processing-in-storage architecture may outperform existing in-storage designs and accelerator-based designs. Multiple performance comparisons for the ReCAM processing-in-storage implementations of $K$ -means and K -nearest neighbors are performed. Compared platforms include CPU, GPU, FPGA, and Automata Processor. We show that PRINS may achieve an order-of-magnitude speedup and improved power efficiency relative to all compared platforms.

From Processing-in-Memory to Processing-in-Storage

Near-data in-memory processing research has been gaining momentum in recent years. Typical processing-in-memory architecture places a single or several processing elements next to a volatile memory, enabling processing without transferring data to the host CPU. The increased bandwidth to and from volatile memory leads to performance gain. However processing-in-memory does not alleviate von Neumann bottleneck for big data problems, where datasets are too large to fit in main memory. We present a novel processing-in-storage system based on Resistive Content Addressable Memory ReCAM. It functions simultaneously as a mass storage and as a massively parallel associative processor. ReCAM processing-in-storage resolves the bandwidth wall by keeping computation inside the storage arrays, without transferring it up the memory hierarchy. We show that ReCAM based processing-in-storage architecture may outperform existing processing-in-memory and accelerator based designs. ReCAM processing-in-storage implementation of Smith-Waterman DNA sequence alignment reaches a speedup of almost five over a GPU cluster. An implementation of in-storage inline data deduplication is presented and shown to achieve orders of magnitude higher throughput than traditional CPU and DRAM based systems.

포맷 변환기를 이용한 화소-병렬 화상처리에 관한 연구

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

Representation of Edmonds' Algorithm for Finding Optimum Graph Branching on Associative Parallel Processors

In the paper, an efficient parallel implementation of Edmonds' algorithm is suggested for finding optimum graph branching on an abstract model of the SIMD type with vertical data processing (STAR machine). For this, associative parallel algorithms for finding critical circuit and its contraction, as well as for unfolding embedded critical circuits, are constructed for directed weighted graphs represented as a list of arcs and their weights. It is shown that the execution of Edmonds' algorithm on a STAR machine requires O(nlogn) time, where nis the number of graph vertexes. Basic advantages of the parallel implementation of Edmonds' algorithm compared to its implementation on sequential computers are discussed.

Comparison of the Prim-Dijkstra and kraskal algorithms on an associative parallel processor

With the help of a model of an associative parallel processor with vertical processing (STAR computer), Prim-Dijkstra and Kraskal algorithms for finding a minimal spanning tree of an undirected graph represented in the form of a list of edges and their weights are compared. A relatively simple representation of the Prim-Dijkstra algorithm is constructed in which the initial node is taken into account. The Kraskal algorithm is also presented and the possibility of eliminating the stage of preliminary sorting of edges by their weights is shown.

A Simple Implementation of Dijkstra's Shortest Path Algorithm on Associative Parallel Processors

In this paper we propose a natural straight forward implementation of Dijkstra's shortest path algorithm on a model of associative parallel processors of the SIMD type with bit-serial (or vertical)...

A Simple Implementation of Dijkstra's Shortest Path Algorithm on Associative Parallel Processors

In this paper we propose a natural straight forward implementation of Dijkstra's shortest path algorithm on a model of associative parallel processors of the SIMD type with bit-serial (or vertical) processing (the STAR-machine). In addition, we show how to extend this implementation for restoring the shortest path from the source vertex to a given vertex. These algorithms of implementation are represented as the corresponding STAR procedures whose correctness is verified and time complexity is evaluated.

Method and apparatus for controlling a digital computer using oral input

Oral input is used to control a digital computer. Associative searching techniques of tabular data structures are used in conjunction with rules and conventions derived from natural language to facilitate the use of oral input. The method is capable of being implemented in connection with conventional sequential computers, associative single-instruction multiple data computers and parallel processors.

Efficient associative algorithm to find the least spanning tree of a graph with a node degree constraint

We have described an associative algorithm to find the smallest spanning tree of a graph with a degree constraint on one of the nodes. The associative algorithm is based on Gabow's algorithm. It is described as a STAR procedure that runs in timeO(@#@ nlogn). This is also the time it takes to construct a minimum spanning tree of a graph on an associative parallel processor [4]. The associative algorithm relies on a number of new constructions that are also useful for other problems. Note that, unlike [13], we use a very simple and natural data representation on an associative parallel processor in the form of two-dimensional binary-coded tables.

System design for pixel-parallel image processing

A system design for performing low-level image processing tasks in real time is presented. The design is based on large processor-per-pixel arrays implemented using integrated circuit technology. Two integrated circuit architectures are summarized: an associative parallel processor and a parallel processor employing DRAM cells. In both architectures, the layout pitch of one-bit-wide logic is matched to the pitch of memory cells to form high-density processing element arrays. The system design features an efficient control path implementation, providing high processing element array utilization without demanding complex controller hardware. Sequences of array instructions are generated by a host computer before processing begins, then stored in a simple controller. Once processing begins, the host computer initiates stored sequences to perform pixel-parallel operations. A programming framework implemented using the C++ programming language supports application development. A prototype system employs associative parallel processor devices, a controller, and the programming framework. Three sample applications, smoothing and segmentation, median filtering, and optical flow, establish the suitability of the system for real-time image processing.

Optimal representation of the minimum spanning tree algorithm in associative parallel processors

Optimal representation of the minimum spanning tree algorithm in associative parallel processors

A 256-element associative parallel processor

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The IXM2 parallel associative processor for AI

Describes the IXM2 associative processor and its main application in speech-to-speech translation. The IXM2 is a semantic memory system machine that began as a faithful implementation of the NETL semantic network machine and grew into a massively parallel SIMD machine that has demonstrated the power of large associative memories. Such processors can support robust performance in speech applications. In fact, the IXM2 with 73 transputers has outperformed a Cray in some language-translation tasks. We selected speech-to-speech translation as our main application because it is one of the grand challenges of massively parallel artificial intelligence. The social implications of successful automatic translation are enormous-e.g. people who speak different languages could communicate in real time by using interpreting telephony. >

An optical associative parallel processor for high-speed database processing. Theoretical concepts and experimental results

We have devised a novel architecture, called the Optical Content-Addressable Parallel Processor for Relational database Processing (OCAPPRP), that exploits the advantages of optics for performing word-parallel and bit-parallel equivalence and relative magnitude searches of database tables in constant time. Moreover, our experimental optoelectronic implementation of the associative processing portion of this architecture has achieved encouraging preliminary results. As the present system evolves, it will substantially exceed current database processing speeds. The proposed architecture has the potential to process approximately 10/sup 10/ tuples per second. Nevertheless, with available optical switching devices such as spatial light modulators (SLMs), the proposed system clearly cannot compete with its electronic counterparts because the switching time of current optical device technology is slow. However, many improvements are being made in optical and optoelectronic device technologies. With advances in SLM technology, we can expect the proposed optical system to become a viable and cost-effective alternative for parallel and high-speed database processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Star ? a language for associative and parallel computation with vertical processing

STAR is a language for coding and analysis of algorithms for associative parallel processors with vertical processing (STARAN type processors). A description of the language is followed by examples of STAR procedures that are used in a model implementation of the superhigh-level language PARIS.

A general-purpose CMOS associative processor IC and system

An associative processor architecture that integrates the functionality of content-addressable memory (CAM), functional memory (FM), and associative parallel processors (APPs) in a single-chip architecture is described. The hardware design, environment and applications of the Coherent Processor, a microchannel memory device designed by combining 16 such chips, are discussed. It is shown that the processor's writable control store permits quick execution of application-specific microcoded operations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Initial evaluation of a parallel associative processor IXM2

This paper describes an initial evaluation of an associative parallel processor, IXM2, for semantic network (SN) applications. IXM2 consists of 64 associative PEs and 9 network PEs, having in total 256 Kwords by 40 bits of associative memory (AM). IXM2 employs a new interconnection mechanism based on complete connection. AM is very effective in suppressing the computational explosion in large SN processing, Arithmetic and logical operations also can be done in parallel on all the words of AM, achieving 7200 MOPS for the less than operation. IXM2 executes programs written in the IXL language, a superset of Prolog. IXM2 can work as a back-end to AI workstations.

A reconfigurable fully parallel associative processor

An associative parallel processing system using novel VLSI associative memory is described. By optimizing the VLSI associative memory architecture, the restrictions that are generally ascribed to classical associative memory systems no longer exist. High performance is achieved without sacrificing memory density due to enhancements in the peripheral circuitry rather than in the storage cell. Using the chip as a basic building block, a dynamically reconfigurable associative processor is proposed. A shifter interconnection network provides the interchip communication required to emulate different networks with a constant routing time for processor data transfers. It also allows for fast communication with a host computer. Parallel arithmetic algorithms are given, together with the application of the Associative Processor to diverse areas such as computer graphics, image processing, and list processing. Results are summarized to show the power of the proposed associative machine which proves to be a general-purpose parallel processor with a broad range of applications.

A 9-kbit associative memory for high-speed parallel processing applications

The authors discuss the design, development and implementation of the 9-kb (256-word*37-bit) associative memory used in the single-chip array processing element (SCAPE) chip, a CMOS VLSI associative parallel processor (APP) that integrates 256 associative processing elements (APEs) on a single 68-pad chip to achieve high-speed, cost-effective image and signal processing. It is shown that a static CMOS content-addressable memory (CAM) design is unsuited to the constraints of the SCAPE chip architecture and that a purely nMOS CAM cell provides the best compromise between the conflicting area, speed, power, and control requirements. Comprehensive details of this design are given together with an evaluation of its performance. Finally, a description of the design methodology used in the construction of the SCAPE chip is presented with a breakdown of circuit areas and operational data.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>