Aspect Ratio TSV Research Articles

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

I ntroduction. High aspect ratio (AR) processes are widely used in front end of line (FEOL) IC manufacturing. Figure 1 depicts high (AR) trench cleaning process. Polymerization residues produced during the dry etch process will cause many problems such as STI voids in the follow-up process if the residues are not removed. This can lead to lower yield and reduction of chip life[1]. It is difficult to completely clean the residue inside trench with aspect ratio greater than 10.As shown in Figure.2, poor wetting of the liquid in the high AR trench, prevents the cleaning of the whole trench. Typically, the wafer surface can be easily cleaned, however residues remain inside of the trench. The cleaning of polymerization residues inside the trench and eliminating watermarks are the main issues in high (AR) cleaning processes. In this paper, we design an infiltration experiment, polymerization residues cleaning experiment and drying experiment to verify single wafer RCA clean performance on high (AR) trench processes. The verification of the single wafer RCA wafer clean is through yield data. Experimental. In the infiltration experiment, a layer of 500A SiO2 was grown on the high aspect ratios trench wafer. As shown in Table I, This was followed by treating the wafers with different process conditions on ACM single wafer tool. The remaining oxide thickness inside trench was measured by transmission electron microscope (TEM). Figure 3 shows experimental steps.In the polymerization residue cleaning experiment, 7 wafers with trenches after dry etching were treated with different chemical and process mode shown in Table II on ACM single wafer tool. The defect count was measured by the inline defect detection equipment and the scanning electron microscope.(SEM)In the drying experiment, high AR wafers were processed on an ACM single wafer tool, under different drying conditions. The trench wafer were then transferred into a vacuum bag and the air was evacuated. If there is no watermark on wafer surface within 15 minutes, we consider that the wafer has been dried in the macro level.Wafers were split between being cleaned by single wafer RCA clean and by bench RCA clean. The wafers are scanned for defect count on the wafer surface after the cleaning process for both the base line (bench) and the single wafer tool. Finally, we review yield on device completion to check results of single wafer and bench clean. Results. Table I shows the result of dHF infiltration experiment. When the pre rinse DIW time exceeds 30 seconds, the whole trench is soaked by DIW, allowing the dHF to permeate the whole trench, with oxide loss being similar from the top to the bottom of the trench.Table II shows the result of cleaning experiment. ACM Single wafer dHF+SC1 (mega) process can effectively clean the whole trench. Figure 4 and 5 shows defect map and SEM picture after single DHF+SC1(mega).Figure 6 shows the effect of chuck rotation speed and N2 flow rate on wafer drying. Figure 10 shows particle performance under different drying process conditions. Figure 7 shows the inline defect map and SEM after dry process.Figure 8 & 9 show the particle performance after the clean process. No special particle map appears with the single wafer clean process. Fig 10 shows the yield performance after all of the processes are completed. Average yield of single clean process is better than the baseline bench clean process. Table 3 shows detailed yield data from the wafer splits . Conclusion. Infiltration and cleaning experiment result shows that single wafer RCA clean can effectively clean the polymerization residues inside of high aspect ratio trenches. Dry experiment result shows that single wafer process can reduce watermark and particles in the dry step. Inline particle performance and final yield performance shows that single wafer RCA clean is better than baseline bench. Single wafer clean has lower standard deviation than bench clean and SW RCA clean in high (AR) trench process is feasible and effective. References. Xue. Research on High Aspect Ratio TSV Cleaning Technology enhanced by Megasonic[D]. Beijing: University of Chinese Academy of Sciences, 2016.JiHoon Cha, ChangSup Mun, etal. Low Si recess on cleaning process by dilute HF/SC-1 with megasonic[J]. Solid State Phenomena, 2008, 134:209-212.H Wang, Yue Ma, Fuping.Chen, etal. Removal of Fine Particle using SAPS Technology and Functional Water[J]. Solid State Phenomena, 2013, 195:185-190.Dae-Hong EOM, Geun-Bae LIM, etal. Reaction of Ozone and H2O2 in NH4OH Solutionsand Their Reaction with Silicon Wafers[J]. Japanese Journal of Applied Physics, 2004, 43:3335-3339. Figure 1

Processing Hundreds of Nanometres Thick Electrografted P4VP for High Aspect Ratio TSV Insulation

In 3D integration of microsystems, electrical insulation of High Aspect Ratio Through Silicon Via (HAR TSV) is a major challenge. This insulation is traditionally realized through the deposition of a thin SiO2 layer. Electrografted poly-4-vinylpyridine (P4VP) has been demonstrated to be considered as an alternative to SiO2 dielectric, traditionally used, for HAR TSVs insulation1. Electrografted P4VP has comparable electrical performances than SiO2 based dielectric and is capable to smoothly cover the scalloped side walls of the TSV with better coverage uniformity than most dielectrics considered for Via-Middle or Via-Last processes2. Electrografting methods are electro-initiated processes. The commercial electrografting solution contains organic reactants in an aqueous acidic media: 4-nitrobezen diazonium (NBD) and monomers of 4 vinylpyridine (4VP). The electrografting mechanism of P4VP onto Si in aqueous media through reduction of diazonium salts is complex. However, a mechanism based on electrochemical initiation followed by a purely chemical polymerization has been proposed. In a first electro-initiated step, aryl radicals must be generated by the electrochemical reduction of NBD on the Si electrode. This can be achieved using different technics such as electrochemical reduction. The generated aryl radicals can covalently bond to the silicon surface through an electron transfer or can initiate radical polymerization of 4VP monomers into P4VP. Most of the published work about electrografting on silicon substrate is realized on oxide free Si-H functionalized surface. Such experimental condition do not usually permit an electrografted polymer to grow up to hundreds of nanometres, which is not suitable to meet electrical requirement for TSV insulation. Experimentally, reverse potential pulse conditions applied on p-type Si-OH functionalized sample allow the electrografting process of P4VP to grow faster and the grafted layer to be thicker. This phenomenon is enhanced if the process is realized under illumination (with the proper wavelength source with the respects of the silicon band gap). One of the hypotheses to explain this increase of kinetic and thickness could be the rapid inversion of the surface charge during the reverse pulse: the polymer structure would stay open by the creation of channels in the film, through desorption of physisorbed species, allowing the reactive species to diffuse more easily from the electrografting solution to the silicon surface. This phenomenon could facilitate the generation of aryl radicals for the 4VP polymerization process to be maintained. And thus, for the P4VP electrografting technic to be a versatile method for HAR TSV electrical insulation. We will present and discuss the electrografting experimental conditions and the impact of the surface preparation on the P4VP to understand their role on the kinetic and the thickness of the grafted P4VP. Acknowledgement Université de Sherbrooke, Natural Sciences and Engeeniring Research Council of Canada (NSERC), Institut National de la Recherche Scientifique (INRS), Teledyne Dalsa and aveni are gratefully acknowledged for their help and their financial support.

(Invited) All-Wet TSV Fabrication Using Electroless Plated Barrier and Cu Seed Layers with Pd Nanoparticle Catalyst

Fabrication of TSV is one of key technologies for 3D-ICs. Filling of Cu electrode materials in a small dimension of TSV is essential for realizing fine-pitch TSVs, which reduce the lisk of thermal stress concentration issues. Cost reduction is also required to be feasible TSVs for a variety of devices. All-wet fabrication of TSVs using electroless plating of barrier and seed is one of solutions to fullfill these requirements. For realizing conformal thin barrier metal layers of Co-alloy or Ni-alloy electroless barriers in a high aspect TSV, Pd nanoparticles as catalyst are very effective because their adsorption is uniform throughout top to bottom of TSV. Furthermore they shows improvements of adhesion between dielectric and metal [1,2]. Adhesion issue is a serious obstacle for electroless plated films in general, however, we found displacement plating of Cu on electroless plated barrier layer has an excellent adhesion property. Finally, we succeeded in formation of a high aspect ratio TSV with superfilled Cu on electroless barrier/seed layers. Reliability aspects relating interdiffusion of Cu against the barrier layers will be discussed further. [1] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, T.Ito, H. Seki, Y.Shinozaki, T.Yamamoto,and S.Shingubara, Electrochimica Acta, 82, 372-377 (2012). [2] F. Inoue, T. Shimizu, H. Miyake, R. Arima, T. Ito, H. Seki, Y. Shinozaki, T. Yamamoto,S.shingubara, Microelectronic Engineering, 106, 164-167 (2013).

Control of 3D IC process steps by optical metrologies

This paper evaluates various optical metrology techniques for in-line control of the uniformity of 3D stacked structures. Advanced packaging technologies are rapidly evolving and 3D architectures require very well controlled process steps. Optical metrology techniques are now used for TSV but also for interconnect processing. In engineering mode, at the process implementation step, these techniques must be evaluated and then used to get uniform and repeatable processes. Among the 3D TSV Via middle process flow, the temporary bonding, wafer thinning and TSV reveal are key 3D process steps to get a uniform backside copper nail signature. High aspect ratio TSV are etched in Front End of the line and deep reactive ion etching systems generates radial non uniformities signatures. The wafer backside processing challenge consists in compensating this issue among the entire wafer surface. In this paper, all these process steps were characterized in order to quantify their specific intra-wafer dispersion signature .of the related key parameters. Cross correlation between the various intra-wafer process step signatures was then analyzed to verify the data set consistency and several process parameters analyzed to get a simple model. This model was then used to get a very uniform copper nail signature. For small diameter TSV and corresponding copper nails, a comparison has been done between full field OCT and confocal chromatic techniques.

Using Graphene As a Conducting Layer and Barrier Layer for High Aspect Ratio through Silicon Via Filling

Traditional process for TSV fabrication is a dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO2 isolation liner; (3) deposition of a TiN barrier layer and a copper seed layer; (4) via fill with copper electrodepositing. Herein, we attempt to use graphene to substitute the TiN barrier layer and the copper seed layer for reducing the traditional process procedure. Graphene materials, including single layer and multi-layer graphene platelet, have recently drawn extensive attention due to their outstanding electrical and thermal properties. Reduction of graphene oxide (GO) is a method to prepare the graphene film. Since GO has a large amount of oxygen functional groups, it can be well dispersed in several solvents and enable it to be coated on a substrate by a chemical grafting method using a wet process. In TSV technology, the thermo-mechanical fatigue may lead to failure in the TSV interconnects because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The packaging materials with different CTEs will induce large stresses at interfaces. To overcome this problem, we choose graphene sheets to substitute the copper seed layer since the CTE of graphene is closer to silicon than copper. In our research, we reduce the procedure of TSV fabrication using a wet process to simultaneously substitute barrier and seed layer with graphene, and to replace filled copper with filled nickel-tungsten alloy in high aspect ratio TSV. This replacement can result in lower fabrication cost compared with the traditional TSV process.

Cu Displacement Plating on Electroless Plated CoWB Layer on SiO2 and Its Adhesion Property

For realizing high aspect ratio TSV with a low cost, the all-wet process utilizing electroless barrier and Cu-seed layers prior to Cu electroplated fill is one of the most promising methods. However, improvement of adhesion property of electroless plated barrier and seed layers on SiO2 has been intensively required. In this study, we studied displacement plating of Cu on electroless CoWB layer formed on SiO2 in an acidic bath. It turned out that displacement-plated Cu film grew with sacrifice of the partial CoWB layer, and showed a high adhesion strength that was enough to pass CMP process.

Control of Adhesion Strength and TSV Filling Morphology of Electroless Barrier Layer

In this study, we investigated to control adhesion property of the electroless plated barrier layer on SiO2 by addition of saccharin and its deposition profile in a high aspect ratio TSV with inhibitor and saccharin. We achieved high adhesion strength of barrier layer by addition of suitable amount saccharin. Furthermore, we succeeded in the formation of thin continuous electroless barrier layer for a high aspect ratio TSV with addition of both inhibitor and saccharin. The proposed highly adhesive and conformal electroless barrier layer formation would provide a highly reliable all-wet TSV filling process.

(Invited) Technologies and Challenges of Fine Pitch Backside Via-Last TSV Process Integration for 3DIC Applications

TSV based 3D stacking IC technology has been aggressively studied recently because of strong benefits in terms of significantly form factor shrinkage, superior system performance (bandwidth & speed), great power reduction, and heterogeneous integration capability. According to different applications, there are different integration options for TSV processing. For high performance 3D system applications which required fine TSV pitch and massive IO connections, how to establish a proper TSV integration scheme became a key importance of enabling 3D IC commercialization. In additional to common foundry used via-middle (VM) process, two another via last approaches, either forming TSV form front-side or backside were also been considered as major TSV process schemes. Although front-side via last (FVL) TSV is widely adopted by OSATs, this scheme is inherently not suitable for fine pitch and high density TSV applications because of significant area penalty and wire routing constraint comparing to VM TSV process. Another backside via last (BVL) TSV process, however, showed many advantages over common VM TSV process while achieving same TSV scalability/density and routing flexibility. For examples: (1) Cu TSVs of BVL were formed after completely CMOS FEOL+BEOL processes, thus it is naturally much less or no Cu pumping out induced yield loss issues comparing to VM process; (2) BVL TSV etching can be stopped on front-side metal 1 layer instead of time etching in blind TSV of VM scheme; (3) No complicated and yield sensitive backside Cu reveal issue were involved; (4) TSV & RDL can be formed together via dual-damascene like processing to simplify process flow and reduce cost of ownership; (5) BVL process can be adopted by either foundry or OSAT manufacturers resulting in most flexible business model in 3DIC supply chain. Despite of the vantage of backside via-last scheme, many process challenges still need to be solved. In this paper, key issues of via middle integration were briefly reviewed. A capable of high aspect ratio and fine pitch TSV (CD … 5um) manufacture scheme was proposed via backside via last integration scheme. Key process technologies and challenges of this BVL scheme, such as temporary bonding, glue material selection, wafer thinning, backside TSV formation, CMP planarization as well as cost reduced TSV/RDL dual damascene flow are investigated.

3D Ics with Embedded Microfluidic Cooling and High Aspect Ratio TSV Integration

Abstract Not Available. Outline: Introduction; Liquid Cooling in 3D ICs; Integration of Electrical TSVs in Microfluidics; and Conclusion

Bath Stability Monitoring for Electroless Cu Seed Formation in High Aspect Ratio TSV

not Available.

Electroless Barrier Deposition with Pd Nanoparticle Catalyst in High Aspect Ratio TSV

not Available.

Via Last using Polymer Liners and their Reliability

This paper discusses the use of polymer dielectrics as insulating liner for realizing two types of 3D-WLP through Si vias (TSV's) in Si wafers with a thickness of respectively 50 and 100μm. These TSV technologies are based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. Key aspects of the TSV processes are: i) fabricating the TSV from the backside of the wafer and contacting to BEOL M1, hence it is independent of the BEOL interconnect stack. ii) use of thick polymer as via isolation is a differentiator from most classical approaches using thin CVD oxide or nitride. The result is a significantly reduced capacitance, and hence, improvement of electrical performance. Another advantage of using thick polymer is that it can absorb some of the stress induced by CTE mismatch between the Cu in via and surrounding Si. This paper presents IMEC's 3D-WLP TSV flavors developed using spin-on dielectric polymers as isolation layer and the reliability of these TSVs' while undergoing thermal cycle tests. For each wafer thickness a 3-mask process sequence is implemented to fabricate the TSVs. Different process flows are used for the different Si thicknesses. For the 100μm thick substrate, a low aspect ratio TSV is used. A Si-via is etched from the wafer backside with a bottom diameter of about 70μm. The top side of the via is chamfered and has a top diameter of about 100μm. As a dielectric liner, a photo-sensitive spin-on polymer is conformally coated on the wafer. At the via bottom, a contact hole with approximately 30μm diameter is realized by photo patterning. Next, conformal Cu plating is used as TSV metallization. For the 50μm thick substrates, a different approach is used enabling a higher aspect ratio TSV. First, a 5μm wide ring trench is etched in the Si. Subsequently, these trenches are filled with a spin-on polymer. After filling the ring trenches, the central Si pillar is etched out of the via (second litho step) and the oxide at the via bottom is removed to provide access to the lowest chip metal level. Next, bottom-up Cu via fill is used to form the TSV metallization. This via has a Cu TSV diameter of 25μm, and an overall diameter with isolation of 35μm [1]. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for maximum post CMOS compatibility The test vehicle used to develop the TSV technologies include TSV daisy chains of various lengths connecting different number of vias to determine the TSV yield and resistance. For both TSV approaches, yielding electrical measurements are done on fabricated TSV wafers. For 50μm thick silicon, up to 95% electrical yield is achieved and the single TSV resistance is measured to be ~10–15mΩ on bonded stacks through Kelvin structures. Thermal cycling from −40 to +125°C of TSV dies are also done, and after 1000 thermal cycles no electrical failure is observed. For 100μm thick silicon TSV approach, single TSV resistance is measured to be ~4–20mΩ with good yield. Test die are subjected to 1000 thermal cycles and results show limited yield loss.