ASIC Research Articles

Flexible Hybrid Integration Hall Angle Sensor Compatible with the CMOS Process

Silicon-based Hall application-specific integrated circuit (ASIC) chips have become very successful, making them ideal for flexible electronic and sensor devices. In this study, we designed, simulated, and tested flexible hybrid integration angle sensors that can be made using complementary metal-oxide-semiconductor (CMOS) technology. These sensors are manufactured on a 100 µm-thick flexible polyimide (PI) membrane, which is suitable for large-scale production and has strong potential for industrial use. The Hall sensors have a sensitivity of 0.205 V/mT. Importantly, their sensitivity remains stable even after being bent to a minimum radius of 10 mm and after undergoing 100 bending cycles. The experiment shows that these flexible hybrid integration devices are promising as angle sensors.

MAC-DNN: An Optimized Hardware Implementation of MAC Unit in Neuron Engine for Deep Neural Network Applications

Object detection and analysis using deep neural networks (DNNs) have become significant challenges due to their computational and power requirements. Hence, such computation is possible on general-purpose platforms like central processing units (CPUs), graphic processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs). However, the development of high computational platforms is a critical challenge for efficient edge computing tasks like object detection, where power and bandwidth are low but faster and energy-efficient solutions are required. System-on-chip (SoC) designs are an optimistic solution for addressing these challenges. This study presents the power and delay-optimized Multiply-Accumulate (MAC) unit architecture for DNN and compares the parameters of 4-bit, 8-bit, 12-bit, and 16-bit MAC units. Vivado software has been employed to construct the MAC unit. It can carry out addition, accumulation, and multiplication operations. The design is analyzed and simulated using the Vivado High-Level Synthesis (HLS) tool, which is subsequently deployed on the Zybo Evaluation and Development Kit. The proposed approach outperforms the existing state-of-the-art models in terms of processing time and power for different precisions.

Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers.

High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, this work focuses on the design and implementation of closed-loop interface ASICs (Application-Specific Integrated Circuits). The proposed interface circuit, based on switched-capacitor modulation technology, incorporates a low-noise charge amplifier, sample-and-hold circuit, integrator, and clock divider circuit. To minimize average power consumption, a switched operational amplifier (op-amp) technique is adopted, which temporarily disconnects idle op-amps from the power supply. Additionally, a class-AB output stage is employed to enhance the dynamic range of the circuit. The design was realized using a standard 0.35 μm CMOS process, culminating in the completion of layout design and small-scale engineering fabrication. The performance of the MEMS accelerometers was evaluated under a 3.3 V power supply, achieving a power consumption of 3.3 mW, an accelerometer noise density below 1 μg/√Hz, a sensitivity of 1.65 V/g, a measurement range of ±1 g, a nonlinearity of 0.15%, a bandwidth of 300 Hz, and a bias stability of approximately 36 μg. These results demonstrate the efficacy of the proposed design in meeting the stringent requirements of high-precision MEMS accelerometer applications.

FLAXE, a SoC readout ASIC for electromagnetic calorimeter at LUXE experiment

The design and qualification results of a System on Chip (SoC) Application-Specific Integrated Circuit (ASIC), called FLAXE, fabricated in 130 nm CMOS technology are presented. FLAXE is a readout ASIC designed for ECAL-p, a compact electromagnetic calorimeter being a part of a detector system for Laser Und XFEL Experiment (LUXE) proposed at DESY, Hamburg, as an extension to the European X-ray Free Electron Laser (XFEL) facility. ECAL-p is a sampling calorimeter with a very compact design targeting small Molière radius, comprising 16 (up to 20) layers composed of 3.5 mm (1 X0) thick tungsten absorber plates interspersed with silicon sensors. Sensor signal is read and shaped by the analogue readout channel, comprising a Charge Sensitive Amplifier (CSA) and a fully differential CR-RC shaper with 50 ns peaking time, which output is digitized in each channel by a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Data from ADC are collected into the ASIC internal memory and read out by the Data Acquisition (DAQ) system between Bunch Crossings (BXs). Around 1000 ASICs have been fabricated and a first batch of 142 ASICs has been packaged and tested. The results of the qualification procedure, as well as measurement result of a single ASIC are presented and discussed.

A high accuracy CMOS peak detection and holder ASIC for neutron detectors

With the completion and operation of a series of high-performance neutron sources, such as the China Spallation Neutron Source (CSNS), various neutron scattering spectrometers have continuously increased their performance requirements. One important aspect is to reduce collisions between scattered neutrons and air molecules during neutron scattering experiments, thereby reducing background noise and obtaining highly accurate experimental measurement results. This paper presents an application-specific integrated circuit (ASIC) dedicated to position-sensitive Helium-3 tubes neutron detector, which introduces peak detection and holder (PDH) circuits on the basis of traditional front-end electronics. Through a specific design, the switches and holding capacitor of the PDH module are isolated, ensuring that the holding voltage is not affected by switch noise, and maximizing the measurement accuracy of the PDH module. The 8 channel ASIC, realized in 0.18 μm CMOS technology, has a 10 fC to 1 pC input signal range with a linearity error within 0.22% to 1%. The PDH module is supplied with a single voltage of 1.8 V with a total power consumption of 350 μW with a layout area of 361 μm × 68 μm. The ASIC further enhances system integration, allowing the analog-to-digital conversion module to employ low-speed ADCs, thereby reducing the overall power consumption of the readout system. This enables the entire detector to operate in a vacuum environment, providing a new electronic readout solution for future neutron scattering and imaging experiments.

Development of a TAC-based TDC in 130 nm CMOS technology

The design and measurement results of a prototype Time-to-Digital Converter (TDC) fabricated in 130 nm CMOS technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in Analog-to-Digital Converter (ADC) design [1]. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional and achieved good Differential Non-Linearity (DNL) and jitter (below 1 LSB), slightly dependent of the selected time precision. The obtained Integral Non-Linearity (INL) is significantly higher than simulated and should be still improved. The prototype Application-Specific Integrated Circuit (ASIC) has configurable time resolution from 15 ps to 140 ps, which gives the total possible time measure range from ±9.5 ns to ±70 ns. In this paper the architecture of the developed TDC is described, comprising the implementation of the Time-to-Analog Converter (TAC) and 10-bit ADC. The measurements of the prototype 8 channel TDC ASIC, showing its linearity and timing resolution are also shown.

A camera for scanning objects in motion based on an integrated detection system working in on-chip TDI mode

The paper presents an X-ray camera for testing moving objects. A typical application of such cameras is scanning products on an industrial production line. Currently, the most popular device detecting radiation in this type of camera consists of a pixel line based on scintillator detectors. Unfortunately, increasing its resolution automatically involves reducing the pixel size and reducing the signal-to-noise ratio. This is where the time domain integration method comes in handy, increasing the resolution without degrading the signal-to-noise ratio. The camera presented in this paper is based on an application-specific integrated circuit dedicated to this purpose. The application-specific integrated circuit core is a pixel matrix operating in a single-photon counting mode. Its architecture was designed to implement the time domain integration method and construct high-resolution cameras with a large scanning area. The article also describes the hardware and software of the application-specific integrated circuit readout system.

On-chip resonance peak extraction in evanescent field silicon photonic biosensors.

Micro ring resonators (MRR) based evanescent field biosensors have shown excellent potential in medical diagnostics due to their performance, scalability, and ability to integrate multiple sensors in a small area to detect various biomarkers simultaneously. The quest to improve the performance and feature size of such sensors has led to the development of cutting-edge photonic integrated circuits (PIC). However, chip-scale implementation of readout and data analysis still needs to be addressed adequately. State-of-the-art evanescent field biosensors rely on off-chip data processing for better results, making the system bulky and ill-suited for point-of-care (PoC) and point-of-use (PoU) applications. In this work, we implement an MRR biosensor in a silicon photonic (SiP) SOI process and demonstrate resonance peak extraction with its measurement data using an application-specific integrated circuit (ASIC) simulated in a 16nm FinFET process with performance similar to external processors.

Optimal Implementation of Tapped Delay Line Time-to-Digital Converters in 20 nm Xilinx UltraScale FPGAs

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM.

High-Precision Digital-to-Time Converter with High Dynamic Range for 28 nm 7-Series Xilinx FPGA and SoC Devices

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively.

PETAT — an ASIC for simple and efficient readout of large PET scanners

Modern PET scanners based on scintillating crystals use solid state photo detectors for light readout. The small area of these devices is beneficial for spatial resolution, but also leads to a large number of electronic channels to be read out, mostly by application specific integrated circuits (ASICs) containing amplification, noise reduction, hit finding, time stamping and amplitude measurement. Although each ASIC provides up to ≈ 64 channels, a large number of chips is required with the need for auxiliary electronic components like voltage regulators or FPGAs for control and data readout. The FPGAs in turn often require multiple supply voltages and configuration infrastructure, so that PCBs get complicated, cumbersome and power-hungry, in addition to the significant power requirement of the front-end ASICs. We address this issue in the latest generation of our PETA readout ASIC for SiPMs by a simplified control scheme and, in particular, by a hierarchical serial data readout which does not require any additional FPGA. In addition, it provides a time-sorted stream of hit data, allowing early on-detector data reduction and hit pre-processing like the removal of hits with no coincident partner. The simplicity of this readout facilitates a supply scheme where power/ground of multiple ASICs are connected in series instead of the standard parallel connection. This `serial-powering' approach can reduce supply current (while increasing overall supply voltage) so that voltage drop issues in the supply are alleviated.

55 μm-pitch indium bump deposition on MEDIPIX single die without using photolithography

Hybrid MEDIPIX detectors are widely used for a variety of applications including scientific experiments at synchrotrons, X-ray Free-Electron-Lasers (XFEL), or with other radiation sources. For many years, MEDIPIX Application-Specific Integrated Circuits (ASIC) and sensors are usually processed on large wafers using a photolithographic lift-off process in order to deposit interconnects such as indium bumps onto the pixel arrays of ASICs and sensors. After deposition, a wafer is singulated into the individual dies and subsequently sensor chips are connected with read-out MEDIPIX ASICs in a flip-chip process. Sensor and ASIC wafers are very expensive and once a process for the hybridization is chosen, a large number of chips are generated having all the same process parameters. For testing process parameters (e.g. flip-chip bonding) or developing detector prototypes, it is desirable to process smaller batches of single dies with a variety of different process parameters. However, applying photolithography to single die with spin-coated photoresist (PR) across the entire die is not a simple task. Due to the large edge bead of the PR, pixels at the periphery of the die will not be processed perfectly. Here we demonstrate a uniform indium bump deposition onto a 256×257 pixel array (55 μm-pitch) of a MEDIPIX individual die using a mechanical masking method that does not require photolithography. Such method will allow testing and optimizing indium bumps on a variety of MEDIPIX chips without processing a large number of expensive wafers. This masking method for single die is compared to the wafer-scale process of indium bump deposition on MEDIPIX ASICs using photolithography.

Conceptual design of TUPI (Timepix4-based Ultra-fast Photon Imaging) detector's hardware

TUPI (Timepix4-based Ultra-fast Photon Imaging) is the new family of direct conversion and vacuum-compatible hybrid detectors under design at Sirius, the Brazilian 4th generation light source. Based on the Timepix4 Application Specific Integrated Circuit (ASIC), it targets different kinds of experiments, such as tomography and spectrometry, and will be used in multiple bioimaging beamlines of Orion, Brazil's Biosafety Level 4 (BSL4) Laboratory project. Also, it will cover a wide energy range (5 to 45 keV) by using different sensors materials (Si, GaAs, CdTe, etc.). Designed in a modular approach to ensure scalability for constructing larger active areas in a compact form, each TUPI module will be composed by a set of 3x side-by-side Timepix4 ASICs to provide a sensitive area of approximately 74×28 mm2 (1344×512 pixels of 55 μm pitch), streaming up to 44 kfps through up to 48×10.24 Gbps optical links directly connected to a Data Acquisition (DAQ) system.

AI-Driven Electrical Fast Transient Suppression for Enhanced Electromagnetic Interference Immunity in Inductive Smart Proximity Sensors.

Inductive proximity sensors are relevant in position-sensing applications in many industries but, in order to be used in harsh industrial environments, they need to be immune to electromagnetic interference (EMI). The use of conventional filters to mitigate these perturbations often compromises signal bandwidth, ranging from 100 Hz to 1.6 kHz. We have exploited recent advances in the field of artificial intelligence (AI) to study the ability of neural networks (NNs) to automatically filter out EMI features. This study offers an analysis and comparison of possible NN models (a 1D convolutional NN, a recurrent NN, and a hybrid convolutional and recurrent approach) for denoising EMI-perturbed signals and proposes a final model, which is based on gated recurrent unit (GRU) layers. This network is compressed and optimised to meet memory requirements, so that in future developments it could be implemented in application-specific integrated circuits (ASICs) for inductive sensors. The final RNN manages to reduce noise by 70% (MSEred) while occupying 2 KB of memory.

Accelerating DTLS on SoC FPGA for secure IoT applications

In the realm of embedded systems and IoT, efficiency and security are among paramount challenges. Datagram Transport Layer Security (DTLS) plays a crucial role in securing IoT communication, but it often imposes significant computational overhead. Stemming from these observations, this study introduces an innovative solution using an System-on-Chip (SoC) Field Programmable Gate Array (FPGA) to address these challenges. Notably, the study effectively demonstrates the integration of DTLS acceleration into the IoT network stack, utilizing the inherent Application-Specific Integrated Circuit (ASIC) cryptographic accelerators embedded within the SmartFusion2 SoC FPGA. The detailed experiments have been conducted for the comparison of the developed hardware with a software implementation of DTLS. The results are remarkable, showcasing substantial gains in key metrics. These improvements include a performance increase of 8 times, a latency reduction of 8.1 times, and a decrease in power consumption of 1.5 times. In summary, this study highlights the crucial role of hardware acceleration, enabled by heterogeneous computing units on a single chip, in enhancing IoT security. The findings underscore the value of SoC FPGAs as an a practical solution for enabling secure IoT communication across a spectrum of IoT applications.

A Survey on Design Space Exploration Approaches for Approximate Computing Systems

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs.

An Encoding ASIC With Real‐Time Correction for Inductive Angular Sensing Systems

ABSTRACTThis article presents an application specific integrated circuit (ASIC) for inductive angular sensing systems, integrating analog‐to‐digital converters (ADCs), digital signal processing (DSP) circuits, and a RISC‐V core on‐chip. The chip, fabricated in a 0.11‐μm CMOS process, is capable of real‐time error correction and angle encoding in response to nonideal factors such as offset, nonlinearity, and noise in the system's sensing signals. This integrated encoding solution could effectively address the issues of large system volume, saving hardware resources while achieving high precision angular measurement. A rotary encoder was additionally developed, utilizing a compact printed circuit board (PCB), which integrates the proposed ASIC, sensing front‐end circuits, and inductive coils. When the on‐chip real‐time correction is enabled, the resolution of the encoder is improved from 0.3516° to 0.0054°, and the nonlinearity error in the 360° range is reduced from 0.5507° to 0.0320°. Besides, the nonlinear error has decreased by more than 90% at different rotation speeds.

Assessment of a space and energy resolved diagnostic based on GEM technology on MAST-U

Abstract A gas electron multiplier (GEM)-based detector was utilized for the first time on a spherical tokamak, MAST-U, during the 2023 campaign to investigate soft x-ray (SXR) radiation (1–20 keV) emitted from the plasma. GEM detectors, chosen for their resilience to harsh fusion environments and their ability to provide energy-resolved ( E r e s ∼ 25 % at 8 keV) SXR emission images (with a spatial resolution of few centimeters) with sub-millisecond time resolution, are a relatively new diagnostic compared to standard semiconductor diodes. In this study, the GEM detector features a pinhole geometry outside the vacuum chamber and observes the plasma through a beryllium window. Filled with an ArCO2 mixture, the detector consists of an Aluminized Mylar cathode, three Aluminum-coated GEM foils, and an anode made of a 16 × 16 matrix of 6 mm2 pads for 2D readout. It employs custom GEMINI ASICs (Application Specific Integrated Circuits) for signal readout, enabling single photon-counting techniques with Time over Threshold analysis on each detector channel, for a maximum rate of 1 MHz per channel. Preliminary results from the 2023 campaign highlight the GEM detector’s ability to complement existing SXR camera systems by adding energy-resolved information to the spatial and temporal data. Case studies demonstrate the detector’s capability to capture Magnetohydrodynamic instabilities, such as Snake instabilities, while utilizing its energy-resolved measurements to analyze plasma events, including Internal Reconnection Events. Additionally, the GEM detector enables the estimation of Electron Temperature in Maxwellian plasmas from SXR measurements. These findings underscore the potential of the GEM-based diagnostic system to enhance the understanding of tokamak plasmas by providing simultaneous spatial, temporal, and energy-resolved insights.

Evaluation and synthesis of perovskite crystals as high-Z sensors for hybrid pixel detectors

High-energy photon imaging experiments are crucial techniques in synchrotron facilities, often employing hybrid pixel detectors for these operations. These detectors combine a photo-sensitive semiconductor component with a pixelated microelectronic Application Specific Integrated Circuit (ASIC) for signal processing and image formation. However, detecting photons above 90 keV poses significant challenges, even for heavy semiconductors, due to lower photoelectric absorption cross-section at this energy range. Nevertheless, lead-based perovskites, such as CsPbBr3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{CsPbBr}}_3$$\\end{document}, are remarkable alternatives as they present excellent cross-section values and noteworthy transport properties, contributing to increased high-energy detection efficiencies. Here, we employ a chemical synthesis route for CsPbBr3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{CsPbBr}}_3$$\\end{document} single-crystals, enabling experimental measurements of carrier mobility of 100.7 cm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{cm}}^{2}$$\\end{document}/Vs. We also developed a simulation algorithm to calculate the current pulses generated on pixelated electrodes. Our simulations evaluate CsPbBr3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{CsPbBr}}_3$$\\end{document}’s performance coupled with the latest photon-counter ASIC developed by CERN, the Timepix4. Our findings indicate that CsPbBr3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{CsPbBr}}_3$$\\end{document} crystals require intense applied electric fields, around 1 kV/mm, for accurate signal integration. Furthermore, we observed no correlation between incident energy and induced pulse width. Through microelectronics simulations, we demonstrate that the signal formation behavior of CsPbBr3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\ ext{CsPbBr}}_3$$\\end{document} is compatible with Timepix4 ASICs, consequently establishing operational guidelines for employing this promising material as sensors in hybrid pixel detectors.

Optimizing embedded AI systems for autonomous driving: Challenges and solutions using bayesian networks

Abstract. Embedded Artificial Intelligence (AI) systems are important components of autonomous vehicles. However, incorporating AI into autonomous vehicles is technically complex, due to the constraints of computation, real-time processing of data, uncertainty handling, and hardware limitations. Bayesian Networks (BNs) are a promising method that allows probabilistic modelling in adaptive learning and environment perception. Here we report on an overview of the application of BNs on autonomous driving, with an emphasis on how BNs can be optimized for embedded system resource constraints, including both computational and energy. Various optimization techniques are discussed, such as model pruning, approximation, acceleration using hardware accelerators, such as Field-Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuit (ASICs), and advanced cooling and power management to ensure AI reliability under high computational load. By reviewing these approaches, we aim to contribute to the development of more robust and green AI systems for autonomous driving.