ASIC Version Research Articles

The XGIS instrument on-board THESEUS: detector principle and read-out electronics

The functionality and experimental performance characterization of the latest four channel version of ORION ASIC, a very low noise multichip read out and processing electronics customized for the X and Gamma Imaging Spectrometer (XGIS) instrument onboard the Transient High-Energy Sky and Early Universe Surveyor (THESEUS) mission, is presented. XGIS is a set of two coded-masked wide field deep sky cameras using monolithic SDDs (Silicon Drift Detectors) and CsI:Tl (Thallium doped-Cesium Iodide) scintillator-based X-γ ray detectors. This paper highlights the design, working principle and the expected performances of the XGIS, on a small scale 2×2 prototype. Furthermore, the evolution timeline of different versions of ORION with detailed performance observations and analysis for spectroscopic resolution, electronic noise and the operational linear energy ranges of both X and the γ processors of the four-pixel ASIC version bonded to a 2×2 SDD array are emphasized. Each 2×2 SDD array element is electrically and dimensionally equivalent to single elements of the THESEUS 8×8 SDD array.

Synthesis of Steel-ASIC, a RISC-V Core

It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.

FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons

With the growing demand for deploying Deep Learning models to the “edge”, it is paramount to develop techniques that allow to execute state-of-the-art models within very tight and limited resource constraints. In this work we propose a software-hardware optimization paradigm for obtaining a highly efficient execution engine of deep neural networks (DNNs) that are based on fully-connected layers. The work's approach is centred around compression as a means for reducing the area as well as power requirements of, concretely, multilayer perceptrons (MLPs) with high predictive performances. Firstly, we design a novel hardware architecture named FantastIC4, which (1) supports the efficient on-chip execution of multiple compact representations of fully-connected layers and (2) minimizes the required number of multipliers for inference down to only 4 (thus the name). Moreover, in order to make the models amenable for efficient execution on FantastIC4, we introduce a novel entropy-constrained training method that renders them to be robust to 4bit quantization and highly compressible in size simultaneously. The experimental results show that we can achieve throughputs of 2.45 TOPS with a total power consumption of 3.6W on a Virtual Ultrascale FPGA XCVU440 device implementation, and achieve a total power efficiency of 20.17 TOPS/W on a 22nm process ASIC version. When compared to other state-of-the-art accelerators designed for the Google Speech Command (GSC) dataset, FantastIC4 is better by 51× in terms of throughput and 145× in terms of area efficiency (GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks

Convolutional Neural Networks (CNN) are widely employed in the contemporary artificial intelligence systems. However these models have millions of connections between the layers, that are both memory prohibitive and computationally expensive. Employing these models on an embedded mobile application is resource limited with high power consumption and significant bandwidth requirement to access the data from the off-chip DRAM. Reducing the data movement between the on-chip and off-chip DRAM is the main criteria to achieve high throughput and overall better energy efficiency. Our proposed multi-bit accelerator achieves these goals by employing the truncation of the partial sum (Psum) results of the preceding layer before feeding it into the next layer. We exhibit the architecture by inferencing 32-bits for the first convolution layers and sequentially truncate the bits on the MSB/LSB of integer and fractional part without any further training on the original network. At the last fully connected layer, the top-1 accuracy is maintained with the reduced bit width of 14 and top-5 accuracy upto 10-bit width. The computation engine consists of an systolic array of 1024 processing elements (PE). Large CNNs such as AlexNet, MobileNet, SqueezeNet and EfficientNet were used as benchmark CNN model and Virtex Ultrascale FPGA was used to test the architecture. The proposed truncation scheme has 49% power reduction and resource utilization was reduced by 73.25% for LUTs (Look-up tables), 68.76% for FFs (Flip-Flops), 74.60% for BRAMs (Block RAMs) and 79.425% for Digital Signal Processors (DSPs) when compared with the 32 bits architecture. The design achieves a performance of 223.69 GOPS on a Virtex Ultrascale FPGA, the design has a overall gain of $3.63 \,\, \times $ throughput when compared to other prior FPGA accelerators. In addition, the overall power consumption is $4.5 \,\, \times $ lower when compared to other prior architectures. The ASIC version of the accelerator was designed in 22nm FDSOI CMOS process to achieve a overall throughput of 2.03 TOPS/W with a total power consumption of 791 mW and with a area of 1 mm $\times \,\, 1.2$ mm.

Readout electronics for LGAD sensors

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

Hardware-Software Implementation of a Sensor Network for City Traffic Monitoring Using the FPGA- and ASIC-Based Sensor Nodes

This paper presents a prototype sensor network for monitoring urban traffic. The sensor network node, equipped with a low-resolution camera, observes the street and detects moving objects. Object detection is based on the custom video segmentation algorithm, using dual background subtraction, edge detection and shadow detection, running on dedicated multi-processor SoC hardware. The number and the speed of the detected objects are transmitted using a low-power license-free radio transceiver to another neighboring node. All the nodes create a self-organized network, data are aggregated at the nodes and passed further to the nodes closer to data sinks. Finally, information about the traffic flow is collected from the sinks and visualized on a PC. The prototype sensor network node has been realized in two versions: FPGA and ASIC. The ASIC version consumes approximately 500 mW and it can be powered from a photovoltaic solar panel combined with a single cell Li-Po battery. The comparison of power consumption of both versions has also been made. Apart from collecting traffic data, the proposed sensor network can gather environmental data, such as the temperature, the acoustic noise or the intensity of the sunlight. The set of 26 prototype sensors has been mounted on street lamp-poles on streets and tested in real conditions.

Cryogenic SiGe ASICs for readout and multiplexing of superconducting detector arrays

This paper presents an ultra low noise instrumentation based on cryogenic electronic integrated circuits (ASICs: Application Specific Integrated Circuits). We have designed successively two ASICs in standard BiCMOS SiGe 0.35 μm technology that have proved to be operating at cryogenic temperatures. The main functions of these circuits are the readout and the multiplexing of TES/SQUID arrays. We report the cryogenic operation of a first ASIC version dedicated to the readout of a 2 × 4 pixel demonstrator array. We particularly emphasize on the development and the test phases of an ultra low white noise (0.2 nV/sqrtHz) cryogenic amplifier designed with two multiplexed inputs. The cryogenic SiGe amplifier coupled to a SQUID in a FLL operating at 4.2 K is also presented. We finally report on the development of a second version of this circuit to readout a 3 × 8 detectors array with improved noise performances and upgraded functionalities.

水晶振動子匂いセンサ用マルチチャンネル高速周波数変化計測回路

Frequency shift measurement circuit with high sampling rate using reciprocal method for QCM odor sensor is proposed. Although the circuit including an analog-type mixer achieved the high sampling rate, the digital mixer in place of analog one is required since all the circuits can be implemented into one chip. The proposed digital mixer helped us achieve 128ms time resolution, 8 times faster than the conventional one, without the deterioration of the frequency resolution. Then, it was found that its introduction into the gas odor visualization system enabled us to have clear image. After the successful implementation into a FPGA, its ASIC version was fabricated. The increase in the mixer performance brought us further increase in the sampling rate of the frequency shift.

RISC design for computer image generation

The paper describes the design and analysis of an instruction set which is applicable to a RISC processor operating as a geometry engine for computer image generation. A prototype LSI implementation of a fixedpoint pipelined RISC is described. It provides a novel technique with DMA channels direct to the register file, a high-performance multiplier and a high-performance divider. The extension of this approach to a VLSI ASIC version using macrocells from a standard cell library is outlined together with a discussion of the testability issues. Results from an LSI implementation and an ASIC simulation are presented.