ASIC Design Research Articles

Design of a Digital Receive Beamformer ASIC Based Ultrasound Imaging System Prototype

This paper presents the design of an eight-channel digital receive beamformer application-specific integrated circuit (ASIC) based ultrasound (US) imaging system. The designed prototype system supports up to 64 transmit and 16 receive channels. ASIC-based 16-channel US transceiver board is designed for frontend processing, and for backend processing Intel[Formula: see text] Core™-i5 based PC is employed. The transceiver board employs two ASICs for digital receive beamforming and a field-programmable gate array (FPGA) for transmit beamforming and system control. The necessary power supplies for the transceiver board are provided by a custom designed and developed high voltage (HV) and low voltage (LV) power supply board. The transceiver board performs the frontend processing like transmit beamforming, control, analog signal conditioning and digital receive beamforming. The received beamformed data are directly transferred to a host PC via the Gigabit Ethernet interface for image formation, post-processing and display. The ASIC-based system developed can provide real-time B-mode imaging with a maximum frame rate of 102 fps with a field of view (FOV) of [Formula: see text]. These results indicate that the ASIC-based US imaging systems can provide better processing capability and performance.

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors to detect charged particles, with the goal to achieve a time resolution of 40–50 ps per hit, and 30–40 ps per track with hits from two detector layers. The ETROC1 is composed of a 5 × 5 pixel array and peripheral circuits. The pixel array includes a 4 × 4 active pixel array with an H-tree shaped network delivering clock and charge injection signals. Each active pixel is composed of various components, including a bump pad, a charge injection circuit, a pre-amplifier, a discriminator, a digital-to-analog converter, and a time-to-digital converter. These components play essential roles as the front-end link in processing LGAD signals and measuring timing-related information. The peripheral circuits provide clock signals and readout functionalities. The size of the ETROC1 chip is 7 mm× 9 mm. ETROC1 has been fabricated in a 65 nm CMOS process, and extensively tested under stimuli of charge injection, infrared laser, and proton beam. The time resolution of bump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in the beam test.

ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption

Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption

Review of Advanced Methods in Hardware Acceleration for Deep Neural Networks

Abstract: Convolutional neural networks have become very efficient in performing tasks like Object Detection providing human like accuracy. However, their practical implementation needs significant hardware resources and memory bandwidth. In recent past a lot of research is being carried out for achieving higher efficiency in implementing such neural networks in hardware. We talk about FPGAs for hardware implementation due to their flexibility for customisation for such neural network architectures. In this paper we will discuss the metrics for efficient hardware accelerator and general methods available for achieving an efficient design. Further, we will discuss the actual methods used by recent research for implementation of deep neural networks particularly for object detection related applications. These methods range from actual ASIC design like TPUs [1] for on chip acceleration, state of the art open source designs like Gemini to methods like hardware reuse, re-configurable nodes and approximation in computations as a trade-off between speed and accuracy. This paper will be a valuable summary for the researchers starting in the field of hardware accelerators design for neural networks

Design of a Sigma-Delta Analog-to-Digital Converter Cascade Decimation Filter

As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB.

ASIC Design and Implementation of Automated Coffee and Tea Brewing System with FPGA Validation

Abstract: This paper presents a pioneering approach to enhance the efficiency of automated coffee and tea brewing systems through the integration of an ASIC-GDSII and FPGA validation. Leveraging the power of 45nm CMOS Technology, the design achieves substantial reductions in area, power consumption, and delay. The Verilog HDL code undergoes meticulous verification using Cadence tools like Genus and Innovus, ensuring optimal design performance. Innovus validates timing constraints, ensuring adherence to acceptable delay parameters. The resulting compact design not only minimizes power consumption but also effectively addresses leakage issues. These comprehensive optimizations meet stringent performance, area, and power requirements, elevating the operational efficiency of automated brewing systems. Furthermore, the control algorithm is synthesized and implemented using Xilinx's ISE Design Suite, followed by validation on SPARTAN 6 FPGA, providing invaluable insights for future synthesis and implementation endeavors.

Evaluation of the effects of K-Means Clustered-Based Weight Quantization on a Keras Library Based Convolutional Neural Network for Hand Written Digit Image Recognition

A lot of Convolutional Neural Networks (CNNs) have been implemented using FPGAs for the past years. Subsequently, memory saving features were added to the CNN through weight quantization using K-means clustering. A future goal on an ASIC design, involving CNN and weight quantization working together in one chip, can give way to an automated procedure of memory-saving CNN design. In this paper an evaluation was done on the effect of quantizing the weights of a Keras library-based CNN using K means clustering. Various values of K in K-means clustering were tested to see its effects on the CNN accuracy performance. This paper presents first the design approach of a Keras library based Convolutional Neural Network (CNN) for hand-written digit images. It then presents a hardware model design of K-Means clustering algorithm using VHDL. The performance of CNN for image recognition was then tested for various levels of weight quantization using K-means clustering algorithm. Simulation results showed a compression of weights as high as 60% resulted to less than 1% reduction in CNN’s accuracy. The findings in this paper will serve as guide in determining the relevant values of K i.e. the compression ratio, for future ASIC design on this topic.

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

Impedance cardiography (ICG) is a rapidly growing non-invasive cardiac health monitoring approach. Synchronous detection of ICG requires an FIR filter to remove the high-frequency carrier signal. Low power consumption and compact area are critical considerations in the design of portable biomedical systems. This paper proposes a novel product quantization-based optimization strategy for the Urdhva Tiryagbhyam Sutra-based multiplier architecture. This paper presents an ASIC design of a low-power and low-area 64th-order programmable FIR filter architecture using the optimized Urdhva Tiryagbhyam Multiplier. The programmable architecture empowers medical practitioners to select the carrier frequency at which the ICG analysis will be performed. The elimination of redundant multipliers from the design based on the filter coefficients is demonstrated. The programmable Vedic FIR filter architecture (described in VHDL) is implemented on the Basys-3 FPGA board for rapid prototyping. The RTL-to-GDSII flow has been completed using Cadence digital design and sign-off tools for the SCL-180 nm technology. The results indicate that the proposed filter architecture occupies 41.33% less area and 42.16% lower power consumption than the contemporary designs described in the literature.

Two HVCMOS active pixel ASIC designs for the Measurement of GCR and SEP with a combined dynamic range of >80 dB

The design of HVCMOS detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) is presented, with the goal of covering a very wide dynamic range (from ∼0.5 fC to pC). Two different pixel designs are shown, one with low gain tailored to high energy depositions and one with high gain for low energy depositions. Both designs utilize a sensing diode consisting of a fully-depleted, high resistivity substrate and a segmented deep n-well on top. LFoundry 0.15 μm technology is used. The design choices are backed by simulation results and preliminary measurements.

Post-Quantum Signatures on RISC-V with Hardware Acceleration

CRYSTALS-Dilithium and Falcon are digital signature algorithms based on cryptographic lattices, which are considered secure even if large-scale quantum computers will be able to break conventional public-key cryptography. Both schemes have been selected for standardization in the NIST Post-Quantum competition. In this work, we present a RISC-V HW/SW codesign that aims to combine the advantages of software and hardware implementations, i.e., flexibility and performance. It shows the use of flexible hardware accelerators, which have been previously used for Public-Key Encryption (PKE) and Key-Encapsulation Mechanism (KEM), for Post-Quantum signatures. It is optimized for Dilithium as a generic signature scheme but also accelerates applications that require fast verification of Falcon’s compact signatures. We provide a comparison with previous works showing that for Dilithium and Falcon, cycle counts are significantly reduced, such that our design is faster than previous software implementations or other HW/SW codesigns. In addition to that, we present a compact Globalfoundries 22nm ASIC design that runs at 800 MHz. By using hardware acceleration, energy consumption for Dilithium is reduced by up to 92.2%, and up to 67.5% for Falcon’s signature verification.

Leveraging Bit-Serial Architectures for Hardware-Oriented Deep Learning Accelerators with Column-Buffering Dataflow

Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions.

Efficient ASIC Architecture for Low Latency Classic McEliece Decoding

Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available “quantum-resistant” systems, the Classic McEliece key encapsulation mechanism (KEM) is positioned as a conservative choice with strong security guarantees. Building upon the code-based Niederreiter cryptosystem, this KEM enables high performance encapsulation and decapsulation and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Classic McEliece operations. Therefore, the present work targets the design, implementation and optimization of a tailored ASIC architecture for low latency Classic McEliece decoding. An efficient ASIC design is proposed, which was implemented and manufactured in a 22 nm FDSOI CMOS technology node. We also introduce a novel inversionless architecture for the computation of error-locator polynomials as well as a systolic array for combined syndrome computation and polynomial evaluation. With these approaches, the associated optimized architecture improves the latency of computing error-locator polynomials by 47% and the overall decoding latency by 27% compared to a state-of-the-art reference, while requiring only 25% of the area.

Development of the Continuous Readout Digitising Imager Array detector

The CoRDIA project aims to develop an X-ray imager capable of continuous operation in excess of 100 kframe/s. The goal is to provide a suitable instrument for Photon Science experiments at diffraction-limited Synchrotron Rings and Free Electron Lasers considering Continuous Wave operation. Several chip prototypes were designed in a 65 nm process: in this paper we will present an overview of the challenges and solutions adopted in the ASIC design.

The data acquisition system for the PANDA Micro-Vertex Detector

The PANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary cluster jet target. The PANDA detector will be composed of several sub-detectors designed for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) is the innermost part of the tracking system surrounding the interaction region, which is designed for precise vertex and tracking detection. It consists of silicon pixel and double-sided microstrip detectors. For the readout of the microstrip sensors an ASIC called ToASt (Torino Asic for Strip readout) is being developed in 0.11 μm CMOS technology at INFN Turin. The ASIC takes advantage of both Time-over-Threshold and Time-of-Arrival methods to accurately measure the event's energy and timestamp. To sustain the acquisition of the microstrip sensors a MDC (Module Data Concentrator) ASIC is under development at KIT. Up to eight ToASt front-ends' data streams are multiplexed, read out and processed by one MDC. The data of several MDCs are collected and processed by the off-detector readout card MMB (MVD Multiplexer Board), also under development at KIT. The processed data is then transferred via 100 GbE optical links to the computing nodes. The ToASt chips have been integrated with the FPGA implementation of the MDC to form the first fully functional detector module. Beam tests have been performed at the COSY facility in Jülich. This paper focuses on the design of MDC ASIC and MMB board, the integration with the ToASt and presents preliminary beam test results.

Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network

Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network

Security Enabled New Term Weight Measure Technique with Data Driven for Next Generation Mobile Computing Networks

In the field of ASIC and FPGA, Machine Learning (ML) techniques play a major role and become predominant for accurate results for different applications like big data analysis and automotive electronics, and driverless vehicles which are required speed and power savings. Due to increasing the demand for higher accuracy, low power, low area consumption, and higher throughput for the complexity of the designs in the latest technology, the proposed system is fulfilling these demands in ASIC and FPGA domains, reconfigurable hardware architecture has been proposed it consists of an ML-based Support Vector Machine (SVM), high-speed AHB protocol and Floating point (FP) operations and also the system has the flexibility to communicate with I2C and I2S protocols. In order to increase throughput with minimal latency, the proposed architecture with AHB protocol and AHB to APB bridge is incorporated between the fabric dynamically reconfigurable multi-processor (FDPM) and peripherals along with security algorithms using SHA-256bits and AES. In order to perform ML-based applications, the proposed system is incorporated double-precision floating point (DPFP) arithmetic operations. The overall proposed architecture is developed in Verilog HDL and quality checking using the LINT tool and Clock Domain Crossing (CDC) using Spyglass tool and synthesized using DC compiler for ASIC and Vivado Design Suite 2018.1 for FPGA implementation and verification. The entire design is interfaced with the Zynq processor and SDK tool to verify data transfer between hardware and software. The obtained results show the generated custom accelerator is able to compute any complex ML classifiers for a larger amount of data. The obtained results are compared with existing state-of-art results and found that 18 % improvement in throughput, a 21 % improvement in power consumption savings, and a 34 % reduction in latency.

The optimization, design and performance of the FBCM23 ASIC for the upgraded CMS beam monitoring system

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment which will replace the present luminometer based on the BCM1F ASIC [1]. The FBCM system should provide reliable luminosity measurement with 1 ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises 6 channels of the fast front-end amplifier working in transimpedance configuration, booster amplifier, and leading edge discriminator. The complete processing chain provides an overall shaping function equivalent to the CR-RC3 filter. The paper will show the optimization of the design, overall architecture, and the detailed implementation in a CMOS 65 nm process as well as preliminary electrical performance.

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

Low-Cost Open Source ASIC Design and Fabrication: Creating your own chips with open source software and multiproject wafers

Low-Cost Open Source ASIC Design and Fabrication: Creating your own chips with open source software and multiproject wafers