Artix-7 FPGA Research Articles

Design and Implementation of a 3-bit ALU with Integrated 7-Segment Display on FPGA

This paper describes the design and implementation of a 3-bit Arithmetic Logic Unit (ALU) with integrated 7-segment display output, deployed on an FPGA platform. The objective of this project is to efficiently perform and display basic arithmetic and logic operations, including addition, subtraction, AND, OR, XOR, and NOT, with an FPGA-based ALU. A control signal selects the operation, and the ALU's 3-bit result is decoded and displayed on a 7-segment interface for clear output visualization. The ALU design is coded in Verilog and includes logic to manage carry and overflow in arithmetic functions. A display decoder module maps the ALU’s binary output to the correct LED segments on the 7-segment display, allowing intuitive real-time readout of operation results. The system was synthesized, simulated, and tested on an Artix-7 FPGA using the Xilinx Vivado development environment, achieving accurate and expected functionality across all operations. This work showcases the effectiveness of FPGA technology in integrating computation and display within a compact digital system, with potential applications in both educational and embedded system design settings where real-time processing and display are essential. Keywords: FPGA, ALU, 7-segment display, Verilog, Digital system design, Embedded computing.

Remote side-channel analysis of the loop PUF using a TDC-based voltage sensor

FPGAs promise significant performance improvements for several computations in cloud applications. However, their shared use in multi-tenant scenarios makes them susceptible to attacks. Different from classical scenarios, where the attacker has hardware access to the device, in cloud scenarios the attack is possible only from remote. As a consequence remote SCA attacks gained increasing attention in the last years. These attacks exploit that attacker and victim share with the same FPGA also the same PDN so that operation-dependent voltage fluctuations caused by the victim’s IP are observable by a voltage sensor of the attacker. While previous attacks in this domain focused on cryptographic algorithms, this work provides insights in an attack on a PUF primitive, the Loop PUF. This primitive is an interesting target for the attack since it might be used, e.g., for storing or deriving secret keys on a remote FPGA. We introduce and discuss the setup of such a remote SCA using a TDC-based voltage sensor. With this sensor, we compare the performance of classical and remote SCA attacks on the Loop PUF using two different Artix-7 FPGA and demonstrate and discuss findings regarding sampling frequency and placement. This work extends and deepens the analysis from a previously published analysis at the ASHES Workshop 2022. In particular, it provides insights into the influence of repeated measurements, measurement time, and usage of multiple TDCs on the attack performance. It also discusses the applicability of the attack to further RO-based PUF primitives. Overall the results show that remote SCA attacks on PUFs in a multi-tenant FPGA scenario have to be considered as a severe attack vector in the future.

Hardware Implementation of a 2D Chaotic Map-Based Audio Encryption System Using S-Box

This paper presents a hardware-based audio encryption system using a 2D chaotic map and dynamic S-box design implemented on an Artix-7 FPGA platform. Three distinct chaotic maps—logistic–fraction (2D-LF), logistic–sine (2D-LS), and fraction–sine (2D-FS)—were investigated and implemented on an FPGA. The 2D-LF map was employed in the encryption system for its throughput and power efficiency performance. The proposed encryption system benefits from the randomness of chaotic sequences for block permutation and S-box substitution to enhance the diffusion and confusion properties of the encrypted speech signal. The system’s encryption strength is validated through performance evaluations, using the mean squared error (MSE), signal-to-noise ratio (SNR), correlation coefficients, and NIST randomness tests, which confirm the unpredictability of the encrypted speech signal. The hardware implementation results show a throughput of 2880 Mbps and power consumption of 0.13 W.

Smart structural health monitoring (SHM) system for on-board localization of defects in pipes using torsional ultrasonic guided waves

Most reported research for monitoring health of pipelines using ultrasonic guided waves (GW) typically utilize bulky piezoelectric transducer rings and laboratory-grade ultrasonic non-destructive testing (NDT) equipment. Consequently, the translation of these approaches from laboratory settings to field-deployable systems for real-time structural health monitoring (SHM) becomes challenging. In this work, we present an innovative algorithm for damage identification and localization in pipes, implemented on a compact FPGA-based smart GW-SHM system. The custom-designed board, featuring a Xilinx Artix-7 FPGA and front-end electronics, is capable of actuating the PZT thickness shear mode transducers, data acquisition and recording from PZT sensors and generating a damage index (DI) map for localizing the damage on the structure. The algorithm is a variation of the common source method adapted for cylindrical geometry. The utility of the algorithm is demonstrated for detection and localization of defects such as notch and mass loading on a steel pipe, through extensive finite element (FE) method simulations. Experimental results obtained using a C-clamp for applying mass loading on the pipe show good agreement with the FE simulations. The localization error values for experimental data analysed using C code on a processor implemented on the FPGA are consistent with algorithm results generated on a computer running Python code. The system presented in this study is suitable for a wide range of GW-SHM applications, especially in cost-sensitive scenarios that benefit from on-node signal processing over cloud-based solutions.

Gaussian Kernel Approximations Require Only Bit-Shifts

An approach to approximate the 2D Gaussian filter for all possible kernel sizes based on the binary optimization technique is introduced. The approximate filter coefficients are designed as negative powers of two, allowing hardware implementation with remarkable savings in the chip area. The proposed approximate filters were evaluated and compared with competing methods using both similarity analysis and edge detection applications. The proposed method and the competing works for masks of size 3×3, 5×5, and 7×7 were implemented in a Xilinx Artix-7 FPGA. The proposed method showed up to a 60.0% reduction in DSP usage and a 75.0% increase in the maximum operating frequency when compared with state-of-art methods for the 7×7 kernel size case and a 48.8% reduction in the dynamic power normalized by the maximum operating frequency.

Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy

Physical unclonable functions (PUF) have significant potential for application in information security. However, strong PUFs are vulnerable to machine learning (ML) modeling attacks, which severely limit their application in device authentication. Despite a variety of resistance techniques, strong PUFs suffer from hardware cost and stability deficiencies. This study proposes an anti-machine-learning-attack strong PUF based on a multi-path delay selection strategy through research on the entropy source of a strong PUF and the delay signal selection mechanism. First, we constructed a deviation source circuit based on multiplexers to increase the diversity of the delay signal transmission paths. Second, we constructed a delay selection circuit based on the logic gates. This circuit dynamically selects the delay signals with the same transmission path in the deviation source using AND and OR gates. Subsequently, the deviation source and delay selection circuits were utilized to construct the delay module, and the interconnection module was inserted between the delay modules to achieve alternating appearances of different types of logic gates along the delay path. Finally, RS flip-flops were employed to make decisions on the bias signals with the same delay path, and the final response was output through an XOR operation. The proposed PUF was implemented on a Xilinx Artix-7 FPGA, and the prediction accuracy of the four typical ML models was below 59 % (with 500,000 challenge-response pairs as the training set). Moreover, the proposed PUF structure is scalable and exhibits better performance in terms of hardware cost and stability than existing classic structures.

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

Hardware implementation of bearing fault diagnosis using empirical mode decomposition

ABSTRACT This paper presents a comprehensive methodology for developing a vibration measurement system, with a primary focus on monitoring rolling element bearings, widely recognised as pivotal components in generic machine vibration monitoring. Through the utilisation of sensors to capture vibration data signals, the system aims to meticulously analyse these signals to discern any indications of bearing health deterioration, thus facilitating the early identification of potential pre-breakdown conditions. The proposed system initiates the process by internally decomposing the three-axis vibration signal, enabling subsequent transmission of processed data to a remote location for the identification of specific faults in the roller element bearings. Installation of a three-axis accelerometer on the bearing housing, positioned radially, facilitates the capture of raw vibration data along one axial and two radial directions. Moreover, efforts to enhance computational efficiency involve cascading multiple identical modules in a serial pipeline structure, allowing for iterative loop computation of intrinsic mode functions within Empirical Mode Decomposition (EMD). Real-time computation is achieved through this serial pipeline structure, necessitating two distinct clock frequencies: one at 12.5 MHz for sampling and storing 3-axis vibration data in ping pong buffers, and another at 40 MHz for reading and processing the data signal retrieved from these buffers. Validation of the proposed method is demonstrated through simulation results obtained via synthesised Verilog code on Xilinx Artix-7 FPGA (XC7A35T-1CPG236C), affirming its efficacy in real-time applications.

Optimizing Energy-Efficient in VLSI Architecture for FIR Filter in Seismic Signal Processing

This project aims to developing an optimized and energy-efficient VLSI design for FIR filters specifically designed for seismic signal processing. The process begins by converting seismic signal dataset values into binary format, and then, simulating them in MATLAB, and generating a coefficient file. This coefficient file is then analyzed using Verilog HDL code and simulated in the Xilinx Vivado 2022.2 tool to assess key parameters such as area, delay, and power. The suggested architecture lessens the complexity of computing, hardware efficiency compared to traditional FIR filters that utilize the CSE technique. This design employs a critical method known as the CSD-based Matrix-Grouped Common Subexpression Elimination (MCSE) algorithm, which significantly reduces the quantity of logic operators (LOs) and logic depths (LDs). Additionally, the design incorporates a Half-Unit Biased (HUB) rounding technique to minimize the truncation errors and cut-set retiming method to reduce the critical-path delay (CPD). This hardware-efficient FIR filter constructs integrates the CSD-based MCSE algorithm, HUB rounding, and cut-set retiming techniques to offer a reconfigurable FIR filter configuration optimized for hardware efficiency, thereby enhancing the real-time alert seismic signal processing. The implementation of an Artix-7 FPGA board including clock gating techniques to further reduces the power consumption.

High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor

This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-Ⅱ unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.

FPGA-BASED IMPLEMENTATION OF A GAUSSIAN SMOOTHING FILTER WITH POWERS-OF-TWO COEFFICIENTS

The purpose of the study is to develop methods for synthesizing a Gaussian filter that ensures simplified hardware and software implementation, particularly filters with powers-of-two coefficients. Such filters can provide effective denoising of images, including landscape maps, both natural and synthetically generated. The study also involves analyzing of methods for FPGA implementation, comparing their hardware complexity, performance, and noise reduction with traditional Gaussian filters. Results. An algorithm for rounding filter coefficients to powers of two, providing optimal approximation of the constructed filter to the original, is presented, along with examples of developed filters. Topics covered include FPGA implementation, based on the Xilinx Artix-7 FPGA. Filter structures, testing methods, simulation results, and verification of the scheme are discussed. Examples of the technological placement of the implemented scheme on the FPGA chip are provided. Comparative evaluations of FPGA resources and performance for proposed and traditional Gaussian filters are carried out. Digital modeling of the filters and noise reduction estimates for noisy images of the terrain surface are presented. The developed algorithm provides approximation of Gaussian filter coefficients as powers of two for a given window size and maximum number of bits with a relative error of no more than 0.18. Implementing the proposed filters on FPGA results in a hardware costs reduction with comparable performance. Computer simulation show that Gaussian filters both traditional and proposed effectively suppress additive white noise in images. Proposed filters improve the signal-to-noise ratio within 5-10 dB and practically match the filtering quality of traditional Gaussian filters.

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

Low-power body-coupled transceiver for miniaturized body area networks

As wearable devices continue to proliferate, seamlessly integrating them into wireless body-area networks (WBANs) becomes increasingly crucial. Body-coupled communication (BCC) emerges as a promising WBAN technology, utilizing the human body itself as a transmission channel. This paper presents a novel BCC transceiver designed for efficiency and miniaturization. The proposed transceiver prioritizes reliable data transmission with a convolutional encoder. It leverages a simple direct digital synthesizer (DDS) for frequency shift keying (FSK) modulation, minimizing chip area. At the receiver, a Viterbi decoder (VD) ensures accurate data recovery. This design shines in its resource efficiency. It occupies less than 1% of an Artix-7 FPGA, operates at 268.77 MHz with a mere 111 mW power consumption, and achieves a remarkable data rate of 13.78 Mbps. This translates to a hardware efficiency of 44.46 Kbps/slice, surpassing existing transceivers. Moreover, the BCC transceiver exhibits a stellar bit error rate (BER) of over 10⁻⁷ under realistic body channel conditions. Overall, this work presents a highly efficient BCC transceiver with significant improvements in chip area, power consumption, and data rate compared to existing designs. This paves the way for practical and miniaturized WBAN solutions for future wearable applications.

Performance Analysis of Approximate Parallel Prefix Adders Realized with Field-programmable Gate Array Technology

Introduction: Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay. Methods: This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits. Results: The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology. Conclusion: This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

TinyM 2 Net-V2: A Compact Low-power Software Hardware Architecture for M ulti m odal Deep Neural Networks

With the evaluation of Artificial Intelligence (AI), there has been a resurgence of interest in how to use AI algorithms on low-power embedded systems to broaden potential use cases of the Internet of Things (IoT). To mimic multimodal human perception, multimodal deep neural networks (M-DNN) have recently become very popular with the classification task due to their impressive performance for computer vision and audio processing tasks. This article presents TinyM 2 Net-V2 —a compact low-power software hardware architecture for m ulti m odal deep neural networks for resource-constrained tiny devices. To compress the models to implement on tiny devices, cyclicly sparsification and hybrid quantization (4-bits weights and 8-bits activations) methods are used. Although model compression techniques are an active research area, we are the first to demonstrate their efficacy for multimodal deep neural networks, using cyclicly sparsification and hybrid quantization of weights/activations. TinyM 2 Net-V2 shows that even a tiny multimodal deep neural network model can improve the classification accuracy more than that of any unimodal counterparts. Parameterized M-DNN model architecture was designed to be evaluated in two different case-studies: vehicle detection from multimodal images and audios and COVID-19 detection from multimodal audio recordings. The most compressed TinyM 2 Net-V2 achieves 92.5% COVID-19 detection accuracy (6.8% improvement from the unimodal full precision model) and 90.6% vehicle classification accuracy (7.7% improvement from the unimodal full precision model). A parameterized and flexible FPGA hardware accelerator was designed as well for TinyM 2 Net-V2 models. To the best of our knowledge, this is the first work accelerating multimodal deep neural network models on low-power Artix-7 FPGA hardware. We achieved energy efficiency of 9.04 GOP/s/W and 15.38 GOP/s/W for case-study 1 and case-study 2, respectively, which is comparable to the state-of-the-art results. Finally, we compared our tiny FPGA hardware implementation results with off-the-shelf resource-constrained devices and showed our implementation is faster and consumed less power compared to the off-the-shelf resource-constrained devices.

Enabling low-latency IoT communication for resource-constrained devices with the led cipher and decipher protocol

Block cipher algorithms are crucial for securing applications on resource-constrained devices. This paper introduces the modified light encryption device (MLED) cipher-decipher architecture, specifically designed to accommodate both 64-bit and 128-bit key sizes while maintaining a consistent 64-bit block and data size. MLED comprises 8-step and 12-step processes for MLED-64 and MLED-128 modules, respectively. Each stage involves a four-round operation followed by an add-round key operation. The add constant module (ACM) and mixed column modules (MCMs) within the round operation have been optimized for improved latency and throughput. Performance analysis reveals that MLED-64/128 requires less than 1% of the available slices and operates at 125 MHz on the Artix-7 FPGA. It achieves delays of 7.5 and 12.5 clock cycles for MLED-64 and MLED-128, respectively, translating to throughputs of 1366.5 Mbps and 819.89 Mbps. Additionally, MLED-64/128 exhibits hardware efficiencies of 2.373 and 0.986 Mbps/slice, respectively. Comparative evaluations with existing LED and other block ciphers (BCs) demonstrate that MLED-64/128 achieves significant improvements in latency, throughput, and efficiency, making it a compelling choice for securing resource-constrained IoT applications.

Agile Acceleration of Stateful Hash-based Signatures in Hardware

With the development of large-scale quantum computers, the current landscape of asymmetric cryptographic algorithms will change dramatically. Today’s standards like RSA, DSA, and ElGamal will no longer provide sufficient security against quantum attackers and need to be replaced with novel algorithms. In the face of these developments, NIST has already started a standardization process for new Key Encapsulation Mechanisms (KEMs) and Digital Signatures (DSs). Moreover, NIST has recommended the two stateful Hash-Based Signatures (HBSs) schemes XMSS and LMS for use in devices with a long expected lifetime and limited capabilities for maintenance. Both schemes are also standardized by the IETF. In this work, we present the first agile hardware implementation that supports both LMS and XMSS. Our design can instantiate either LMS, XMSS, or both schemes using a simple configuration setting. Leveraging the vast similarities of the two schemes, the hardware utilization of the agile design increases by 20% in LUTs and only 3% in Flip Flops (FFs) over a standalone XMSS implementation. Furthermore, our approach can easily be configured with an arbitrary number of hash cores and accelerators for the one-time signatures for different application scenarios. We evaluate our implementation on the Xilinx Artix-7 FPGA platform, which is the recommended target for PQC implementations by NIST. We explore potential tradeoffs in the design space and compare our results to previous work in this field.

A Compact Hardware Design and Implementation on FPGA Based Hybrid of AES and Keccak SHA3-512 for Enhancing Data Security

Data security means protecting important information from unauthorised persons. In a security system, cryptography is the most secure method. Cryptography has many kinds, but the Advanced Encryption Standard (AES) is the most secure system. If combined with AES and Secure Hash Algorithm-3-512Bits (SHA3-512), it becomes compact, more secure, and more authenticated for data communications. The proposed methodology is a hybrid cryptography technique that combines AES with the SHA3-512 algorithm. This system becomes a strong, secure system and produces a strong cipher text. The proposed method AES/SHA3-512 is Hardware implementation on the Artix-7 FPGA family yields the lowest cost and highest hardware efficiency with a reduction in area usage of LUT 18.49%, Flip Flops 0.83%, and IO 3.8%. The proposed architecture is synthesised and simulated using the Vivado 2017.2 version Tool.

FPGA IMPLEMENTATION OF ADAPTIVE ZERO-TRACKING ALGORITHM FOR REAL-TIME DOA ESTIMATION USING A LINEAR ANTENNA ARRAY

In this paper, we employed blind separation techniques to estimate the direction of arrival (DOA) in a smart antenna system. Indeed, we have processed the antenna’s output signal through the Symmetric Pre-Whitening algorithm in order to isolate each incident wave. Since we are interested by defining the DOA of strongest wave, we have characterized each separated wave using the power spectral density. The most powerful wave is then modeled by a three order autoregressive model whose complex zeros, computed and tracked adaptively, will be plotted in the unit circle. After convergence of the zero-tracking process, we assumed that the DOA corresponds to the phase of the zeros whereas the radius will give an idea on its magnitude. To assess the efficiency of the developed method in real-time, we compared the simulation results with those obtained from implementing the Symmetric Pre-Whitening and zero-tracking algorithms on the Artix-7 FPGA board. The results obtained by simulation and hardware implementation are quite similar.

Unsupervised deep learning framework for temperature-compensated damage assessment using ultrasonic guided waves on edge device

Fueled by the rapid development of machine learning (ML) and greater access to cloud computing and graphics processing units, various deep learning based models have been proposed for improving performance of ultrasonic guided wave structural health monitoring (GW-SHM) systems, especially to counter complexity and heterogeneity in data due to varying environmental factors (e.g., temperature) and types of damages. Such models typically comprise of millions of trainable parameters, and therefore add to cost of deployment due to requirements of cloud connectivity and processing, thus limiting the scale of deployment of GW-SHM. In this work, we propose an alternative solution that leverages TinyML framework for development of light-weight ML models that could be directly deployed on embedded edge devices. The utility of our solution is illustrated by presenting an unsupervised learning framework for damage detection in honeycomb composite sandwich structure with disbond and delamination type of damages, validated using data generated by finite element simulations and experiments performed at various temperatures in the range 0–90 °C. We demonstrate a fully-integrated solution using a Xilinx Artix-7 FPGA for data acquisition and control, and edge-inference of damage. Despite the limited number of features, the lightweight model shows reasonably high accuracy, thereby enabling detection of small size defects with improved sensitivity on an edge device for online GW-SHM.