Hardware Implementation of a 2D Chaotic Map-Based Audio Encryption System Using S-Box

Abstract

This paper presents a hardware-based audio encryption system using a 2D chaotic map and dynamic S-box design implemented on an Artix-7 FPGA platform. Three distinct chaotic maps—logistic–fraction (2D-LF), logistic–sine (2D-LS), and fraction–sine (2D-FS)—were investigated and implemented on an FPGA. The 2D-LF map was employed in the encryption system for its throughput and power efficiency performance. The proposed encryption system benefits from the randomness of chaotic sequences for block permutation and S-box substitution to enhance the diffusion and confusion properties of the encrypted speech signal. The system’s encryption strength is validated through performance evaluations, using the mean squared error (MSE), signal-to-noise ratio (SNR), correlation coefficients, and NIST randomness tests, which confirm the unpredictability of the encrypted speech signal. The hardware implementation results show a throughput of 2880 Mbps and power consumption of 0.13 W.