Art FPGA Research Articles

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors

Modern High Level Synthesis (HLS) tools succeed well in their engineering productivity goal, but still require toolset and target technology specific modifications to the source code to guide the process towards an efficient implementation. Furthermore, their end result is a fixed function accelerator with limited field and runtime flexibility. In this paper we describe the status of AEx, a novel work-in-progress HLS tool developed in the FitOptiVis ECSEL JU project. AEx is based on automated exploration of architectures using a flexible and lightweight parallel co-processor template. We compare its current performance in CHStone C-language benchmarks to the state of the art FPGA HLS tool Vitis, provide ASIC implementation numbers, and identify the main remaining toolset features that are expected to dramatically further improve the performance. The potential is explored with a hand-optimized case study that shows only 1.64x performance slowdown with the programmable co-processor in comparison to the fixed function Vitis HLS result.

Most Resource Efficient Matrix Vector Multiplication on FPGAs

Fast and resource-efficient inference in artificial neural networks (ANNs) is of utmost importance and drives many new developments in the area of new hardware architectures, e.g., by means of systolic arrays or algorithmic optimization such as pruning. In this paper, we present a novel method for lowering the computation effort for ANN inference utilizing ideas from information theory. Weight matrices are sliced into submatrices of logarithmic aspect ratios. These slices are then factorized. This reduces the number of required computations without compromising on fully parallel processing. We create a new hardware architecture for this dedicated purpose. We also provide a tool to map these sliced and factorized matrices efficiently to reconfigurable hardware. By comparing to the state of the art FPGA implementations, we can prove our claim by lowering hardware resources measured in look-up-tables (LUTs) by a factor of three to six. Our method does not rely on any particular property of the weight matrices of the ANN. It works for the general task of multiplying an input vector with a constant matrix and is also suitable for digital signal processing beyond ANNs.

FPGA-based real-time data processing for accelerating reconstruction at LHCb

In run-3, beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities. One such solution is a highly-parallelized custom tracking processor (“Artificial Retina”), implemented in state of the art FPGA devices connected by fast serial links. We describe the status of a realistic prototype for the reconstruction of pixel tracking detectors that will run on real data during run-3.

Iterative Retina for High Track Multiplicity in a Barrel-Shaped Tracker and High Magnetic Field

Real-time track tracking in high energy physics experiments at colliders running at high luminosity is very challenging for trigger systems. To perform pattern-recognition and track fitting in online trigger system, the artificial Retina algorithm has been introduced in the field. Retina can be implemented in the state of the art FPGA devices. Our developments use Retina in an iterative way to identify track for barrel-shape tracker embedded in a high magnetic field and with high track multiplicity. As a benchmark we simulate LHC t-tbar events, with a pile-up of 200 and a GEANT-4 based simulation of a 6-layers barrel tracker detector made of silicon modules. With this sample the performance of the hardware design (resource usage, latency) is evaluated. Both efficiency and purity of the Retina fitting are over 90%. Moreover we have also added a Kalman filter after the Retina fit to improve the resolution on the track parameters. Our simulation results show that the Kalman filter can work well together with the Retina algorithm to find track through t-tbar event and provides high resolutions of the reconstructed parameters.

A Correlation-Less Approach Towards Adaptive Channel Equalizer Based on Wiener–Hopf Equation

Wiener, the well-known adaptive filter is seen in almost all the applications of adaptive signal processing. It gets the weight updating by solving the Wiener –Hopf equation (ωopt = R−1P). When implemented on the state of the art hardware, like ACIS or FPGA, this filter results in substantial resource consumption. This paper proposes updating the filter weights by reducing the need for an auto-correlation matrix (R) and calculating the filter weights based on cross-correlation vector (P) only. This approach would result in a noticeable resource reduction by compromising some of the performance that may be acceptable in voice or video being less sensitive. The proposed correlation-less approach and the conventional method are first simulated in Matlab and then is implemented in Xilinx Vertex 7 FPGA for one to one comparison. The results indicate that the proposed approach reduces a significant amount of resources along with acceptable performance characteristics. Therefore, it may be incorporated in various applications of mobile communication, especially the adaptive channel equalizer.