Ring Oscillator Array Research Articles

Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \text {T} = +{300}^{\circ }\text{C}$ </tex-math></inline-formula> in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal. Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs “on-line” to prolong their useful lifetime towards a more sustainable use.

System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array

Counterfeiting has unfortunately become a worldwide epidemic affecting electronic systems from consumer goods to military equipment, which seriously jeopardizes system security, reliability, and electronic vendors’ reputation. The counterfeit parts, e.g., integrated circuits (ICs) and printed circuit boards (PCBs), have shown a significant increase in type and number over the recent years. However, the existing counterfeit detection techniques deal with IC or PCB separately, and hence, they cannot verify the authenticity of an electronic system as a whole. In this paper, we propose concurrent IC and PCB authentication (CIPA), a novel methodology that concurrently verifies the authenticity of both IC and PCB through extracting the signature pairs generated by a ring oscillator (RO) array without/with PCB cavity resonance. With CIPA, remote authentication is allowable by transmitting the signatures between the verifier and the system vendor. The CIPA structure has shown insignificant area overhead (0.945% on average) when implemented on a number of benchmarks. Both CIPA and the benchmarks have been implemented on the authentic and counterfeit FPGA systems, and the results give 100% confidence in detecting counterfeit ones. Furthermore, the authenticity of PCB and IC (i.e., authentic or counterfeit) of the system under test can also be mined from CIPA signatures. According to the experimental results, systems composed of different authenticity states of PCB and IC are differentiated from each other with the confidence of 97.62%. The overall authentication time is $40.2~\mu \text{s}$ considering 50-MHz system clock.

Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators

A space-filling clock tree is presented, which takes an advantage of LC resonant clocking, to obtain a uniform phase and amplitude multiply-by-3 clock from a unique Sierpinski-coupled ring oscillator (SCRO) array. The three-stage interleaved SCROs resemble the Sierpinski triangle, and are synchronized with a common frequency to all. The SCRO further provides an aligned output phase relationship to reduce skew. The triangle clock grid with a side length of 3.2 mm is filled by a space-filling clock tree. The 3-D stacked transformers at the tree endpoints extract the third harmonic of the SCRO array oscillation and scale the voltage amplitude of the extracted clock. The transformers also perform a built-in bandpass filtering function to remove injected noise. An experimental prototype integrated in a 90-nm CMOS operates at 2.85–4.3 GHz and consumes 19.2–49 mW under 0.7–1 V supply voltages. With 300-mV added supply noise, jitter was measured as 3.4 ps (rms) and 17.7 ps (pp). The measured results reveal substantial improvements in both power and jitter from this approach.

Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit

The impact of random telegraph noise (RTN) on circuit delay has been experimentally verified using a dual ring oscillator (ROSC) array test structure. The proposed on-chip monitor utilizes the tested-and-proven beat frequency detection technique to measure RTN-induced frequency shifts with high precision (>0.01%) and short sampling time (>1 $\mu \text{s}$ ). The main idea is to pair an ROSC in the first array with an ROSC having a similar frequency from a second array, so that the frequency measurement resolution is not compromised at sub-0.5-V supply voltages. RTN-induced frequency shifts at different supply voltages, temperatures, and stress conditions were measured from a 32-nm high-k metal-gate test chip. The impact of RTN on logic and SRAM performance was analyzed based on the measured RTN data. We also present the quantitative results of logic timing margin and SRAM noise margin, with and without RTN. According to this paper, RTN appears to have a modest 1% impact on circuit operating frequency in 32 nm, even under pessimistic conditions (i.e., $V_{\mathrm {dd}} = 0.6$ V, multiple RTN traps in circuit path).

(Invited) Low-Temperature Sol-Gel Derived Ultra-Flexible Metal-Oxide Thin-Film-Transistors and Their Applications

Solution-processed metal-oxide thin-film transistors (TFTs) were fabricated for flexible integrated circuits. As gate dielectric layer, a transparent insulating oxide, ZAO (Zirconium incorporated aluminum oxide) has been employed instead of using pristine AlOx (Aluminum oxide). Using the ZAO gate dielectric, field-effect mobility of 6.21 cm2/Vs and hysteresis-free property have achieved by improving the interface between the gate dielectric and the IGZO (Indium gallium zinc oxide) semiconductor layer. For the surface modification, a heterogeneous ZAO gate dielectric has been used. With the IGZO TFTs employing ZAO gate dielectric, an ultra-flexible 7-stage ring-oscillator array was fabricated.

Low timing-jitter and high precise delay generation with coupled ring oscillators

A novel design of delay generator based on a coupled ring oscillators is investigated; it attains a delay resolution near a fully differential buffer delay divided by the number of rings. A three-input fully differential buffer constructed with shunting three N-type metal-oxide-semiconductor field-effect transistors is employed for the coupled ring oscillators. The coupling structure forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a fully differential buffer delay. Experimental results with Taiwan Semiconductor Manufacturing Company 0.35 μm-process technology demonstrate that the delay generator can achieve an output delay resolution of 163 ps at the operating frequency of 245 MHz with low timing-jitter of 75 ps.

A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop

Resource estimation of a power distribution network (PDN) is a critical issue for the resource management of LSIs. To evaluate the impact of PDN parameters to the quality of power delivery, an accurate PDN simulation model is necessary. To reflect the real silicon's behavior to PDN simulation models, we propose a test structure that consists of an array of Ring Oscillators (ROs) with calibration circuits for static IR-drop measurement. The calibration circuit is used for the estimation of the RO frequency without any IR-drops so that we can estimate the absolute value of the IR-drop under circuit operation. A test chip which includes 540 ROs and 270 calibration circuits is fabricated in a 65 nm process. The maximum discrepancy between the measurement and simulation values is 0.18% in standby mode, and 0.76% for additional current loading mode.

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip.

Fabrication of polymer-based electronic circuits using photolithography

We exploited the concept of solvent orthogonality to enable photolithography for high-resolution, high-throughput fabrication of electronic circuits based on a polymeric semiconductor. An array of ring oscillators utilizing top contact polymer thin film transistors with 1 μm channel length has been fabricated on a 100 mm wafer scale. We used high performance, air stable poly(2,5-bis(thiophene-2-yl)-(3,7-ditri-decanyltetrathienoacene) as our active semiconducting material. Owing to the small channel length and small overlap length, these devices have a signal propagation delay as low as 7 μs/stage.

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization

Variations in the number and characteristics of charges or traps contributing to transistor degradation lead to a distribution of device “ages” at any given time. This issue is well understood in the study of time dependent dielectric breakdown, but is just beginning to be thoroughly addressed under bias temperature instability (BTI) and hot carrier injection (HCI) stress. In this paper, we present a measurement system that facilitates efficient statistical aging measurements involving the latter two mechanisms in an array of ring oscillators. Microsecond measurements for minimal BTI recovery, as well as frequency shift measurement resolution ranging down to the error floor of 0.07% are achieved with three beat frequency detection systems working in tandem. Measurement results from a 65 nm test chip show that fresh frequency and the stress-induced shift are uncorrelated, both the mean and standard deviation of that shift increase with stress, and the standard deviation/mean ratio decreases with stress time.

Technology Variability From a Design Perspective

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.

Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.

CMOS Ring Oscillator Array with Dual Connections

The novel CMOS ring oscillator array focused attention on the adjacent relationship between the component oscillators is proposed. Compared with the conventional CMOS ring oscillator array, the proposed oscillator array has the bi-directional connections. To verify the operation of the proposed oscillator, using 1.2μmCMOS Level 3 models, the circuit simulations are performed.

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Precise delay generation using coupled oscillators

A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay resolution equal to a buffer delay divided by the number of rings. The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay. The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages. Experimental results from a 2- mu m N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps. >