Array Block Research Articles

A novel broadband low backscattering antenna array based on integration of absorptive and coding metasurface

AbstractThis paper presents a low‐scattering 1 × 2 patch array antenna combining resistive and coding metasurfaces (MSs) for the reduction of wideband‐backscatter. An artificial magnetic conductor technology is used to validate the proposed technique, which is fundamentally based on scattering, phase cancellation, and absorptive property of the MS. By integration of coding MS elements and an absorbent unit cell, three different array blocks are utilized to significantly reduce the monostatic and bistatic backscattered energy level from 6.5 to 16.5 GHz, as well as overall reduction from 5 to 22 GHz. Under the incidence of plane waves, various reflection phases have been observed. The diffusion of the scattering energy from the surface can be achieved by carefully choosing the phase distributions for the reflected waves. Additionally, the bistatic backscattered energy level of the prototype is realized at various frequency points. This technique is validated using artificial magnetic conductors, which uniquely combine the effects of scattering, phase cancellation, and absorption in the MS's hybrid unit cells. Further, antenna array parameters are optimized for frequency, polarization, and angular diversity, S‐parameters, radiating efficiency, reducing radar cross section (RCS) in the wideband range and ensuring robust performance. The experimental results were substantiated by simulations of the reference and proposed prototypes suggesting that the proposed prototype can be a good candidate for applications that require a low monostatic and bistatic RCS platform.

3D Lightweight Cryptosystem Design For IoT Applications Based On Composite S-Box

The security of the Internet of Things (IoT) depends on strong cryptographic functions that require extensive computation and resources. The security of Internet of Things (IoT) relies on the use of strong cryptographic functions that demand extensive computation and resources. Therefore, the selection of a cryptographic system is influenced by the computational and communicational capabilities of IoT devices, including their energy requirements, memory constraints, and execution time. This paper aims to develop a lightweight and secure encryption algorithm for IoT applications, focusing on advancing cryptanalysis techniques. We propose a new lightweight algorithm named enhanced 3D RECTANGLE, designed to deliver robust security for IoT applications and optimized for cell phones with minimal memory usage, low power consumption, and efficient performance. The RECTANGLE block cipher was chosen for this research due to its high efficiency and speed relative to other lightweight algorithms, despite some security issues. The proposed enhanced 3D RECTANGLE algorithm improves confusion and diffusion properties through a new 3D array block rotation method for 4x4 plaintext, based on a 128-bit key and 16 rounds. Additionally, we designed a 4x4 composite S-Box with a Galois field pipelining structure, offering a more advanced solution compared to the Look-Up Table method. The cryptanalysis, avalanche effect, and bit error rate tests were conducted to verify the security strength of the proposed algorithm. The proposed algorithm was evaluated against two existing algorithms, RECTANGLE and Extended 3D RECTANGLE. The enhanced 3D RECTANGLE algorithm provides better cryptanalysis, demonstrating a 40% avalanche effect and achieving a bit error rate (BER) of 31%, indicating its greater effectiveness compared to the other two lightweight algorithms.

GMiner++: Boosting GPU-based frequent itemset mining by reducing redundant computations

Frequent itemset mining (FIM) is increasingly important in fundamental data mining techniques. However, the applicability of existing FIM methods is limited, mainly because of their performance. The expected performance improvement is limited owing to the exploitation of only a single thread, despite numerous efficient single-threaded FIM methods being proposed. Numerous parallel FIM methods have been devised using graphic processing units (GPU) or multicore central processing units (CPUs) to overcome the shortcomings of these methods. However, when extracting patterns from large amounts of data, multi-threaded FIM methods exhibit a similar performance tendency to single-threaded FIM methods, because of their large memory footprints and computations. Hence, we propose GMiner++, a memory-efficient GPU-based FIM method equipped with several GPUs. We propose a sub-database of the same size called bit array blocks, which contains pre-calculated bit arrays of F1∪P(IK). These bit arrays are repeatedly exploited during mining tasks using an elegant probabilistic model. GMiner++ can obtain frequent patterns and use several GPUs only by using the bit array blocks and the occurrence update scheme. The proposed method decreased redundant computations using pre-calculated bit arrays with bit array blocks. In addition, GMiner++ does not create intermediate data during mining tasks to increase robustness and reduce memory footprints. Simulation results demonstrate that GMiner++ outperformed existing FIM methods concerning performance and scalability with increasing robustness.

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder

DRAM latency has remained almost constant over decades and has become a performance bottleneck of computing systems. In this study, we propose a low-cost DRAM architecture enabling dynamic reconfiguring of row decoder to provide reduced latency with high flexibility and reliability. We apply minimum changes to row decoders and allow dynamic reconfiguration to switch array blocks between two modes: 1) normal mode, where the DRAM array behaves in the same manner as the conventional DRAM does and 2) low latency mode, where two DRAM cells in the neighbor array blocks are coupled to operate as a logical cell and reduce latency reliably according to the differential principle. On the basis of an industrial open bitline (BL) cell array, we only change the word-line decoding scheme but keep the cell array and sense amplifiers (SAs) untouched to avoid modifications to the DRAM process for cost and reliability considerations. Our circuit simulation shows that the low-latency mode can reduce row-to-column delay and row access strobe time by 25.7% and 23.2%, respectively. We evaluate the reduced-latency LPDDR4 DRAM on various workloads. Compared with the JEDEC standard DRAM, our proposal provides a maximum system performance improvement of 8.5%. We believe that our proposal is a reliable and cost-friendly solution to DRAM latency reduction.

The performance study of developed cost-effective Compton Camera based on Ce:GAGG scintillator using experimental measurements and CCMod of GATE simulation module

In our previous work, a cost-effective Compton camera (CC) using Ce doped Gd3(Al,Ga)5O12(Ce:GAGG) scintillator consisting of two detectors, scatterer (20.8 × 20.8 × 5 mm3) and absorber (41.7 × 41.7 × 10 mm3), was developed to image gamma rays having energy more than 511 keV. This study fabricated a newly developed CC with a larger scatterer and thinner absorber. The system consists of two detectors: a scatterer and an absorber of Ce:GAGG scintillator. The size of the scatterer and absorber is the same; a 40-mm × 40-mm × 5-mm array block consists of 40 × 40 pixels. The size of each scintillator pixel is 0.85 mm × 0.85 mm for both systems. Imaging experiments of Na-22 and Cs-137 point sources were performed to investigate the imaging capability of the new camera, and then the obtained data were compared to the previous CC. The current CC's absolute detection efficiency (DE a ) and photopeak detection efficiency (DE p ) are improved by 1.6 and 2 times greater than the previous one. At the same time, both systems' spatial and angular resolutions are almost the same value at 511 keV. The Compton camera module (CCMod) in GATE v9.0 was employed for Monte Carlo simulations to reproduce the experimental data showing a good agreement.

Strategy of Mitigating Breakdown Interference and Yield Loss in Crossbar Memory

The fault devices induced by device breakdown (BD) are unavoidable due to defect formation during fabrication or along with device cycling stress. The BD cells not only deteriorate device yield, but they also introduce sneak current and result in cell-to-cell interference in the high density crossbar array, which further produces severe array yield loss. Although the BD interference is important, methods of alleviation is less discussed. In this work, we evaluate the strategy of mitigating the strong interference between normal cells and leaky BD cells. We show that while a sufficiently high device yield is the prerequisite, optimizing cell parameters such as resistance of the BD cell and line resistance are proven crucial. However, the yield loss induced by BD interference is not easily compensated using naive redundancy designs. Therefore, a careful optimization on array partition is thus required. We show that with a device yield of 99% and a total memory capacity of megabits, partitioning into a smaller array size (<128 x 128) provides a higher area density than that into larger array sizes. Finally, we proposed a testing bias scheme to rapidly evaluate the device and array yields with an n-time speedup in test latency for an n x n array. The proposed testing bias scheme provides an effective way of ruling out inappropriate low-yield arrays in a memory bank with multiple array blocks.

Detection of Technical Errors and Construction Optimization for Custom Tissue Arrays at Transplanting and Casting

Purpose: The purpose of this research is to identify causes for the most common typical defects in the production of tissue arrays at the most crucial stages, and to optimize protocols for custom-made tissue arrays at variable input parameters and different final requirements. In this way, we can avoid difficult repairs of tissue arrays, at which, because of re-allocation, major losses can occur, including destruction of the sample due to mechanical and thermal effects.&#x0D; Methods: Seven hundred and twenty tissue array blocks were included, some for clients and others for experimentation and protocol refinement. Human and animal tissue were used. We tested and evaluated configurations, structural stability, consistency, stability, and practical usability of such designed tissue arrays under different laboratory physical conditions.&#x0D; Results: We recognized and analyzed 12 mistakes in the production of tissue arrays in the histology laboratory during the stages of transplantation and casting. At each examined error we found the causes, gave suggestions for prevention, and provided instructions on how to eliminate or prevent those causes.&#x0D; Conclusion: Problems have solutions that are technically feasible but they require individual adjustments of laboratory procedures, time, and learning. This is more difficult or even impossible for automated laboratories, as in the described handmade tissue arrays. However, all laboratories need to produce with maximum quality and precision, which is possible only with addressing problems regularly. The results of this study will contribute to the optimization of custom made tissue array processes.

Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM

In a conventional open bit-line scheme of DRAM, the edge subarrays (MATs) located at both ends of the cell array block contain alternated real and dummy bit-lines, unavoidably leading to an additional area overhead. To reduce the area overhead, one edge MAT can be eliminated by converting the dummy bit-lines of the other edge MAT into real bit-lines. This strategy causes the conventional bit-line sense amplifiers (BLSAs) in the MATs located at both ends of the cell array block to have a much smaller complementary bit-line capacitance than a true bit-line capacitance. Thus, the sensing operation of a conventional BLSA with this unbalanced bit-line capacitance experiences various problems: sensing voltage decrease, data flipping, and asymmetric equalization. To solve these problems, we propose a novel sensing circuit that can operate effectively even under unbalanced bit-line capacitance, thus suggesting the possibility of an open bit-line scheme without dummy bit-lines. Our proposed dummy-less open bit-line scheme can save approximately 4% of the array height. Compared with the conventional unbalanced BLSA, the proposed BLSA increases the sensing voltage by more than 100%, reduces the voltage peaks by 30% during the data transfer, and reduces equalization time by 1.2 ns in HSPICE Monte Carlo simulation.

Design and Simulation of Improved Soft Computing Based MPPT for Solar PV System Under Variable Irradiance Condition

Renewable energy sources are becoming more common in the energy generation field these days. Renewable energy sources such as photovoltaic (PV) systems, wind power (WP), and biomass are gaining popularity due to their ease of use, low cost, and low environmental impact. The environmental issues, declining fuel supplies, and increasing energy demands have drawn our attention to the glimmer of hope for a future focused entirely on sustainable and non-polluting energy sources. Photovoltaic (PV) power generation is becoming more common in comparison to other renewable energy sources due to advantages such as ease of access, low cost, low environmental emissions, and lower maintenance costs. In this dissertation, three separate Maximum power point monitoring techniques are used to construct a solar PV system (MPPT). Modeling and simulation using the MATLAB Simulink programmeare being used to check the effectiveness of the proposed scheme. The model is investigated using two partial shading patterns. By providing different values of input radiations to all four modules connected in sequence, we were able to create partial shading conditions using the PV array block. The panel's output is fed to the optimization technique block, which then feeds the boost converter from their duty cycle output. Under partial shading, the results show that the Particle Swarm Optimization algorithm outperforms the Perturb and Observe and Incremental Conductance algorithms..

Fpga Implementation of Precise Convolutional Neural Network for Extreme Learning Machine

Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require more computation time. Extreme Learning Machines (ELM’s) are time-efficient, and they are less complicated than the conventional gradient-based algorithm. In previous years, an SRAM based convolutional neural network using a receptive – field Approach was proposed. This neural network was used as an encoder for the ELM algorithm and was implemented on FPGA. But, this neural network used an inaccurate 3-stage pipelined parallel adder. Hence, this neural network generates imprecise stimuli to the hidden layer neurons. This paper presents an implementation of precise convolutional neural network for encoding in the ELM algorithm based on the receptive - field approach at the hardware level. In the third stage of the pipelined parallel adder, instead of approximating the output by using one 2-input 15-bit adder, one 4-input 14-bit adder is used. Also, an additional weighted pixel array block is used. This weighted pixel array improves the accuracy of generating 128 weighted pixels. This neural network was simulated using ModelSim-Altera 10.1d and synthesized using Quartus II 13.0 sp1. This neural network is implemented on Cyclone V FPGA and used for pattern recognition applications. Although this design consumes slightly more hardware resources, this design is more accurate compared to previously existing encoders.

Evaluation of epidermal growth factor receptor mutations and thyroid transcription factor-1 status in Turkish non-small cell lung carcinoma patients: A study of 600 cases from a single center.

This study aims to investigate the frequency, distribution, and morphological/immunohistochemical features of epidermal growth factor receptor mutations and to examine the possible relationship between the material type and technical success of mutation analysis in Turkish population with non-small cell lung cancer. Between September 2012 and December 2015, a total of 499 consecutive, treatment-naïve patients (437 males, 163 females; mean age 61 years; range, 30 to 84 years) with primary or metastatic non-small cell lung cancer who underwent epidermal growth factor receptor mutation testing using Sanger sequencing method were retrospectively analyzed. Archival records and hematoxylin-eosine and immunohistochemically stained sections were re-examined. The thyroid transcription factor-1 and napsin A immunohistochemical stains were performed on tissue array blocks. Seventy-five mutations were detected in 70 patients (14%). The success rate of testing and intact deoxyribonucleic acid fragment length were significantly higher in the cytological material, compared to tissue specimens (p<0.001). The mutation rate in adenocarcinomas was 33.9% for women and 9.4% for men. The most common mutation was L746-E750del in exon 19 (29.3%), followed by the L858R mutation in exon 21 (28%). The mutation rate was the highest in micropapillary (40%) and lowest in solid (5.4%) adenocarcinomas. All epidermal growth factor receptor mutations, except for one, were positive for the thyroid transcription factor-1. The single nucleotide polymorphism Q787Q in exon 20 was observed in 79.6% of patients. The frequency and distribution of epidermal growth factor receptor mutations in the Turkish patients with non-small cell lung cancer are similar to the European populations. These results also demonstrate that cytological materials are highly reliable for epidermal growth factor receptor mutation testing, and the probability of detection of wild-type epidermal growth factor receptor is low in cases of thyroid transcription factor-1 negativity.

INTERLEAVING BURST ERROR ELEMENTS IN INFORMATION ARRAYS USING THE METHOD OF INDEX STRUCTURISATION

Objectives. “Burst errors” representing groups of accidentally or intentionally distorted or “erased” characters in blocks of information arrays violate the integrity of their content. However, the use of special codes for detecting and correcting such errors significantly reduces the speed of information transfer due to the need to introduce redundancy in the form of a large number of control characters. Therefore, this study sets out to develop a method for correcting burst errors.Method. A possible approach for correcting burst errors consists in interleaving preliminary permutations of information array elements between different array blocks. After eliminating the results of element permutations, these procedures cause the interleaving of distorted elements occurring during the transfer or storage of the information array between its various blocks, causing single or minor fold errors.Result. For solving problems of this class, a new method of permuting elements of an nxnset of finite sets is proposed based on the index structuring of the formed configurations. These sets are interpreted as information arrays of the same configuration, and the permutation – interleaving – of their elements is carried out according to the method of configuration formed by the index structuring of their location.Conclusion. Three methods for interleaving elements of the original information in arrays are proposed: between rows, between columns and combined – between rows and columns. The proposed interleaving methods based on the preliminary conversion of information arrays by permuting elements according to given algorithms allow their distortions under the influence of burst errors to be corrected. Thus, the task of combating the burst errors leading to the destruction of individual groups of characters can be reduced to solving a simpler problem of minor fold error correction.

ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement

Placement has always been the most time-consuming part of the field programmable gate array (FPGA) compilation flow. Conventional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range-limiting strategy for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The experimental results are based on the Titan benchmarks, which contain 4K to 30K blocks, including logic array blocks, inputs and outputs, digital signal processors, and random access memories. This approach achieves $2.82\boldsymbol \times $ speed up, 4.8% reduction on wire length, 4.1% improvement on critical path compared with the SA from VTR with wire length-driven optimization, and $1.78\boldsymbol \times $ speed up, 10% reduction on wire length, 2% reduction on critical path with path timing-driven optimization. It also manifests better scalability on larger benchmarks.

Performance Evaluation of 1.5 kV Solar Inverter With 2.5 kV Silicon Carbide mosfet

1.5 kV dc link voltage has been a trend for the solar industry. Moving from 1 to 1.5 kV dc voltage can increase string length, enhance inverter conversion ability, increase array block sizes, and improve performance. Multilevel converters are the natural choices while control becomes more complicated. If a simple two-level converter is adopted, the 1.7 kV device may not be applicable considering the voltage derating for certain failure rate. Therefore, devices with higher blocking voltage should be considered. This paper reports for the first time the performance characterization of a 2.5 kV silicon carbide (SiC) mosfet . The potential application of this device for 1.5 kV solar inverter is also evaluated compared to the solutions with a 1.2 kV device.

RATE INCREASE OF THE OBJECTS CLASSIFICATION ON THE CONVOLUTIONAL NEURAL NETWORKS WITH THE SELF-ORGANIZATION MAPS IMPLEMENTATION

Objects and processes classification is a common experimental problem. Its solution, first of all, is needed in automatic diagnosis systems, for example, to determine the equipment operation state through the diagnostic signal or to identify abnormalities with medical images. With the development of convolutional neural networks, new prospects for solving such problems have risen up. However, the classification accuracy that can be achieved on these networks is not sufficient enough for all diagnosis issues. It is subject to, for example, timely diagnosis of the onset of transient phenomena. At the same time, another type of neural network, Kohonen self-organizing maps, has a conceptual property for training on unclassified set of classes, that is, giving the opportunity to solve such an issue. Therefore, the accuracy enhancement of the classification on the basis of Kohonen networks implementation in the architecture of convolutional networks is a relevant objective and has practical significance. The article analyzes the means of improving the accuracy of convolutional neural networks and arising problems solution. The ways of increasing the proportion of correct clustering on Kohonen networks due to the ‘growth’ of its grid shape in determining new classes in the learning process are also given. It is this property that makes it possible to recognize transient phenomena. It is determined that the existing solutions of the combination of Kohonen networks and convolutional networks are aimed at improving the efficiency of only self-organizing maps, with the purpose to improve the accuracy of classification by convolutional networks, it became necessary to develop a new architecture. The paper provides a description of this issue. Since the initial information of the Kohonen networks is the weighting matrix values of the grid shape neurons, it was necessary to associate it with the representation of the images in order to process the diagnostic images. The paper proposes the concept of a built-in associative array block based on Kohonen networks. According to the proposed method, a software implementation of a hybrid neural network is developed. The formulation and results of computational experiments are presented. The efficiency of the proposed method is experimentally proved. Keywords: convolutional neural networks, CNN, Kohonen self-organizing maps, SOM, signal classification, image classification.

Uso de la técnica de micromatrices de tejido en histología veterinaria

Las micromatrices de tejido son plataformas de alto rendimiento que permiten el análisis de decenas a cientos de muestras de tejidos en forma simultánea. Estas se han utilizado, en especial, para analizar tejidos neoplásicos. Sin embargo, los beneficios de su aplicación pueden ser aprovechados en otras áreas de investigación, como la embriología y la histología. El presente trabajo explora el uso de la técnica de micromatrices de tejido para el análisis morfológico y molecular de tejidos animales normales. Un total de 82 muestras de piel canina normal prenatal y posnatal fueron utilizadas para construir la matriz. A partir de ésta, se obtuvo una gran cantidad de secciones en las que se aplicaron técnicas de histología convencional y de inmunohistoquímica. Los resultados nos muestran la eficacia de la técnica para realizar el análisis morfológico y molecular de decenas de muestras de tejido normal en forma simultánea. Esto permite la evaluación más estandarizada de los tejidos, reduciendo así la variabilidad que puede ocurrir cuando se realizan ensayos sobre muestras individuales.

High energy X-ray pinhole imaging at the Z facility.

A new high photon energy (hν > 15 keV) time-integrated pinhole camera (TIPC) has been developed as a diagnostic instrument at the Z facility. This camera employs five pinholes in a linear array for recording five images at once onto an image plate detector. Each pinhole may be independently filtered to yield five different spectral responses. The pinhole array is fabricated from a 1-cm thick tungsten block and is available with either straight pinholes or conical pinholes. Each pinhole within the array block is 250 μm in diameter. The five pinholes are splayed with respect to each other such that they point to the same location in space, and hence present the same view of the radiation source at the Z facility. The fielding distance from the radiation source is 66 cm and the nominal image magnification is 0.374. Initial experimental results from TIPC are shown to illustrate the performance of the camera.

Wafer-level fabrication of a high-silica v-groove for fiber-optic packaging using deep dry-etching with a dual-frequency high-density plasma

We developed a procedure for fabricating deep silica v-grooves of about 70 μm for fiber-optic applications by using a deep dry-etching with a dual-frequency high-density plasma source. This procedure has the advantages of sub-micron precision with wafer-level productivity and a high etching speed of 0.7 μm/sec. An electro-plated hard mask as thick as 8 μm that can endure the deep dry-etch was also developed. In particular, the angular inclination of the etched groove was controllable by using the flow of C4F8 gas. A fiber array block was assembled by using a v-groove chip. The location error of the fiber cores in the block was measured to be less than 0.3 μm. This confirms that the dry-etched silica v-grooves can be applied to the packaging of optical devices with wafer-level productivity and high precision.

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Abstract This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Imaging of radiocesium uptake dynamics in a plant body by using a newly developed high-resolution gamma camera

We developed a new gamma camera specifically for plant nutritional research and successfully performed live imaging of the uptake and partitioning of 137Cs in intact plants. The gamma camera was specially designed for high-energy gamma photons from 137Cs (662 keV). To obtain reliable images, a pinhole collimator made of tungsten heavy alloy was used to reduce penetration and scattering of gamma photons. A single-crystal scintillator, Ce-doped Gd3Al2Ga3O12, with high sensitivity, no natural radioactivity, and no hygroscopicity was used. The array block of the scintillator was coupled to a high-quantum efficiency position sensitive photomultiplier tube to obtain accurate images. The completed gamma camera had a sensitivity of 0.83 count s−1 MBq−1 for 137Cs with an energy window from 600 keV to 730 keV, and a spatial resolution of 23.5 mm. We used this gamma camera to study soybean plants that were hydroponically grown and fed with 2.0 MBq of 137Cs for 6 days to visualize and investigate the transport dynamics in aerial plant parts. 137Cs gradually appeared in the shoot several hours after feeding, and then accumulated preferentially and intensively in growing pods and seeds; very little accumulation was observed in mature leaves. Our results also suggested that this gamma-camera method may serve as a practical analyzing tool for breeding crops and improving cultivation techniques resulting in low accumulation of radiocesium into the consumable parts of plants.