Strategy of Mitigating Breakdown Interference and Yield Loss in Crossbar Memory

Abstract

The fault devices induced by device breakdown (BD) are unavoidable due to defect formation during fabrication or along with device cycling stress. The BD cells not only deteriorate device yield, but they also introduce sneak current and result in cell-to-cell interference in the high density crossbar array, which further produces severe array yield loss. Although the BD interference is important, methods of alleviation is less discussed. In this work, we evaluate the strategy of mitigating the strong interference between normal cells and leaky BD cells. We show that while a sufficiently high device yield is the prerequisite, optimizing cell parameters such as resistance of the BD cell and line resistance are proven crucial. However, the yield loss induced by BD interference is not easily compensated using naive redundancy designs. Therefore, a careful optimization on array partition is thus required. We show that with a device yield of 99% and a total memory capacity of megabits, partitioning into a smaller array size (<128 x 128) provides a higher area density than that into larger array sizes. Finally, we proposed a testing bias scheme to rapidly evaluate the device and array yields with an n-time speedup in test latency for an n x n array. The proposed testing bias scheme provides an effective way of ruling out inappropriate low-yield arrays in a memory bank with multiple array blocks.