ARM Cortex-M3 Research Articles

RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference

Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to reduce the computational overhead at the HD inference phase, we introduce a pruning method to remove the ineffectual dimensions. The proposed pruning method can reduce the dimension from 10k to 1k with negligible accuracy loss. Second, an ISA extension for RI5CY is proposed to compute the HD inference efficiently. Experimental results indicate that RISC-HD adds <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.42\times $ </tex-math></inline-formula> area overhead to the RI5CY core; however, it consumes only 2932 slices on the Artix-7 FPGA, which is suitable for resource-constrained devices. Additionally, RISC-HD improves the total clock cycle by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.48\times $ </tex-math></inline-formula> compared to the RI5CY core and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.17\times $ </tex-math></inline-formula> compared to ARM Cortex-M4 in the ISOLET data set. Moreover, RISC-HD achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.22\times $ </tex-math></inline-formula> energy efficiency compared to the RI5CY core.

Low Latency Implementations of CNN for Resource-Constrained IoT Devices

Convolutional Neural Network (CNN) inference on a resource-constrained Internet-of-Things (IoT) device (i.e., ARM Cortex-M microcontroller) requires careful optimization to reduce the timing overhead. We propose two novel techniques to improve the computational efficiency of CNNs by targeting low-cost microcontrollers. Our techniques utilize on-chip memory and minimize redundant operations, yielding low-latency inference results on complex quantized models such as MobileNetV1. On the ImageNet dataset for per-layer quantization, we reduce inference latency and Multiply-and-Accumulate (MAC) per cycle by 22.4% and 22.9%, respectively, compared to the state-of-the-art mixed-precision CMix-NN library. On the CIFAR-10 dataset for per-channel quantization, we reduce inference latency and MAC per cycle by 31.7% and 31.3%, respectively. The achieved low-latency inference results can improve the user experience and save power budget in resource-constrained IoT devices.

Find the Bad Apples: An efficient method for perfect key recovery under imperfect SCA oracles – A case study of Kyber

Side-channel resilience is a crucial feature when assessing whether a postquantum cryptographic proposal is sufficiently mature to be deployed. In this paper, we propose a generic and efficient adaptive approach to improve the sample complexity (i.e., the required number of traces) of plaintext-checking (PC) oracle-based sidechannel attacks (SCAs), a major class of key recovery chosen-ciphertext SCAs on lattice-based key encapsulation mechanisms (KEMs). This new approach is preferable when the constructed PC oracle is imperfect, which is common in practice, and its basic idea is to design new detection codes that can determine erroneous positions in the initially recovered secret key. These secret entries are further corrected with a small number of additional traces. This work benefits from the generality of PC oracle and thus is applicable to various schemes and implementations.Our main target is Kyber since it has been selected by NIST as the KEM algorithm for standardization. We instantiated the proposed generic attack on Kyber512 and then conducted extensive computer simulations against Kyber512 and FireSaber. We further mounted an electromagnetic (EM) attack against an optimized implementation of Kyber512 in the pqm4 library running on an STM32F407G board with an ARM Cortex-M4 microcontroller. These simulations and real-world experiments demonstrate that the newly proposed attack could greatly improve the state-of-the-art in terms of the required number of traces. For instance, the new attack requires only 41% of the EM traces needed in a majority-voting attack in our experiments, where the raw oracle accuracy is fixed.

A Faster Third-Order Masking of Lookup Tables

Masking of S-boxes using lookup tables is an effective countermeasure to thwart side-channel attacks on block ciphers implemented in software. At first and second orders, the Table-based Masking (TBM) schemes can be very efficient and even faster than circuit-based masking schemes. Ever since the customised second-order TBM schemes were proposed, the focus has been on designing and optimising Higher-Order Table-based Masking (HO-TBM) schemes that facilitate masking at arbitrary order. One of the reasons for this trend is that at large orders HO-TBM schemes are significantly slower and consume a prohibitive amount of RAM memory compared to circuit-based masking schemes such as bit-sliced masking, and hence efforts were targeted in this direction. However, a recent work due to Valiveti and Vivek (TCHES 2021) has demonstrated that the HO-TBM scheme of Coron et al. (TCHES 2018) is feasible to be implemented on memory-constrained devices with pre-processing capability and a competitive online execution time. Yet, currently, there are no customised designs for third-order TBM that are more efficient than instantiating a HO-TBM scheme at third order.In this work, we propose a third-order TBM scheme for arbitrary S-boxes that is secure in the probing model and under compositions, i.e., 3-SNI secure. It is very efficient in terms of the overall running time, compared to the third-order instantiations of state-of-the-art HO-TBM schemes. It also supports the pre-processing functionality. For example, the overall running time of a single execution of the third-order masked AES-128 on a 32-bit ARM-Cortex M4 micro-controller is reduced by about 80% without any overhead on the online execution time. This implies that the online execution time of the proposed scheme is approximately eight times faster than the bit-sliced masked implementation at third order, and it is comparable to the recent scheme of Wang et al. (TCHES 2022) that makes use of reuse of shares. We also present the implementation results for the third-order masked PRESENT cipher. Our work suggests that there is a significant scope for tuning the performance of HO-TBM schemes at lower orders.

SoK: SCA-secure ECC in software – mission impossible?

This paper describes an ECC implementation computing the X25519 keyexchange protocol on the Arm Cortex-M4 microcontroller. For providing protections against various side-channel and fault attacks we first review known attacks and countermeasures, then we provide software implementations that come with extensive mitigations, and finally we present a preliminary side-channel evaluation. To our best knowledge, this is the first public software claiming affordable protection against multiple classes of attacks that are motivated by distinct real-world application scenarios. We distinguish between X25519 with ephemeral keys and X25519 with static keys and show that the overhead to our baseline unprotected implementation is about 37% and 243%, respectively. While this might seem to be a high price to pay for security, we also show that even our (most protected) static implementation is at least as efficient as widely-deployed ECC cryptographic libraries, which offer much less protection.

Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers

The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to the nature of the hardware-friendly design of SPEEDY, the algorithm has low performance for software implementations. In particular, 6-bit S-box and bit permutation operations of SPEEDY are inefficient in software implementations, where it performs word-wise computations. We implemented the SPEEDY block cipher on a 32-bit microcontroller for the first time by applying the bit-slicing techniques. The optimized encryption performance results on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e., cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. In RISC-V, the performance showed 81.9, 95.5, and 109.2 clock cycles per byte, which outperformed the previous works. Finally, we conclude that SPEEDY can show efficient software implementation on low-end embedded environments.

ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Side-channel attacks are powerful attacks for retrieving secret data by exploiting physical measurements, such as power consumption or electromagnetic emissions. Masking is a popular countermeasure as it can be proven secure against an attacker model. In practice, software-masked implementations suffer from a security reduction due to a mismatch between the considered leakage sources in the security proof and the real ones, which depend on the microarchitecture. We propose ARMISTICE, a framework for formally verifying the absence of leakage in first-order masked implementations taking into account modeled microarchitectural sources of leakage. As a proof of concept, we present the modeling of an Arm Cortex-M3 core from its RTL description and leakage test vectors, as well as the modeling of the memory of an STM32F1 board, exclusively using leakage test vectors. We show that, with these models, ARMISTICE pinpoints vulnerable instructions in real-world masked implementations and helps the design of masked software implementations which are practically secure.

Portable electronic nose system with elastic architecture and fault tolerance based on edge computing, ensemble learning, and sensor swarm

The portable electronic nose (E-nose) systems are suffering from the limited computing ability of microcontrollers and can only adopt simple pattern recognition algorithms. The heavy coupling between the sensors greatly limits the anti-fault ability of the system. Herein, a novel ensemble learning framework based on independent artificial neural networks (ANN) is proposed in a portable E-nose system to recognize volatile organic compounds (VOCs). Edge computing is applied to complete data processing and analysis on an ARM Cortex-M3 based microcontroller in an E-nose system. Each sensing unit can recognize VOCs by training independent ANN models. Then an ensemble learning method further organizes the diverse ANN models into an onboard sensor swarm with a significantly enhanced performance. The accuracy of the type classification can reach 81.1%, which is improved by more than 20% compared with the best individual classifier. The R2 score of concentration prediction can reach 84.1%, which is improved by more than 25% compared with the best regressor in the ensemble group. For both type identification and concentration prediction, the tolerance to the sensor faults of swarm-based E-nose is 10 and 18 times greater than that of the conventional array-based sensors, respectively. Our work has designed an elastic architecture based on sensor swarms, providing a novel avenue for the development of E-nose systems with high fault tolerance.

A Current Sensorless Control of Buck-Boost Converter for Maximum Power Point Tracking in Photovoltaic Applications

In the present paper, a current sensorless (CSL) method for buck-boost converter control is proposed for maximum power point tracking (MPPT) photovoltaic applications. The proposed control scheme uses the mathematical model of the buck-boost converter to derive a predefined objective function for the MPPT control. The proposed scheme does not require any current sensor and relies only on the input voltage signal, which decreases the implementation cost. The proposed method is successfully implemented using a Matlab/Simulink/Stateflow environment, and its effectiveness is compared over the perturb and observe (P&amp;O) method. An experimental rig, that includes a buck-boost converter, a PV simulator, and a resistive load, is used for the experimental validation. A rapid Arduino prototyping platform is used for the digital implementation, where the SAM3X8E microcontroller of the Arduino DUE board, which integrates an ARM Cortex-M3 MCU, is used as a target hardware for the proposed model-based controller developed under the Stateflow environment. Furthermore, the integrated pulse width modulation (PWM) macrocell is used to generate accurate PWM gate-drive signals for the buck-boost converter. Compared to the P&amp;O, the presented simulation and experimental results show that the proposed method has reduced the computation burden and the sensor cost of implementation by 24.3%, and 27.95%, respectively.

An Auto-Encoder Based TinyML Approach for Real-Time Anomaly Detection

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Condition monitoring plays a crucial role in the automotive space because they reduce the downtime and maintenance costs by preventing sudden catastrophic breakdown of vehicles. Condition monitoring solutions primarily monitor onboard sensor data to detect anomalies. However, with vehicles becoming more complex each day, the number of sensors to be monitored is also growing. This increases the data volume to be processed to make decisions. It is not feasible to send all the embedded sensor data captured to the cloud for processing. The network bandwidth, latency for transferring the data and finally the cost associated with data transfer are the factors which impede us from taking this approach. Much of the previous work done to address these issues has proposed Deep Learning driven onboard anomaly detection approaches. The deployment of these implementations requires power hungry and costly hardware with high computational resources. The recent advances in the field of Tiny Machine Learning have made it possible to design and deploy Deep Neural Networks on resource constrained low-cost embedded hardware. In this paper, we propose an Auto-Encoder based approach for anomaly detection in time-series vibration sensor data. The designed Auto-Encoder model has a 7.5 KB footprint and was finally deployed on a highly resource constrained ARM Cortex-M4 microcontroller with 256KB of SRAM and 1MB Flash. The model has been validated on the previous machine data. It has achieved an accuracy and precision close to 80%. Currently, by using post training quantization we are trading-off model accuracy for a reduction in model size. In future, we plan to use Quantization Aware Training which will help us in achieving even higher model accuracy.&lt;/div&gt;&lt;/div&gt;

Faster NTRU on ARM Cortex-M4 With TMVP-Based Multiplication

This paper focuses on speeding up NTRU - one of the lattice-based finalists of the NIST PQC competition - by improving the ring multiplication. The Number Theoretic Transform (NTT), Toom-Cook, and Karatsuba are the most commonly used algorithms for implementing NTRU. In this paper, we propose Toeplitz matrix-vector product (TMVP) based algorithms for multiplication for all parameter sets of NTRU. We implement the proposed algorithms on ARM Cortex-M4. The results show that the TMVP-based multiplication algorithms we propose are more efficient than the others in the literature in most cases. Our algorithm for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ntruhps2048509</i> outperform the Toom-Cook and NTT methods in the literature by 25.4% and 21.5%. We also observe the impact of these improvements on the overall performance of NTRU. We speed up the key generation, encryption, decryption, encapsulation, and decapsulation algorithms of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ntruhps2048509</i> by 12.5%, 14.3%, 17.7%, 3.9%, and 14.7%, respectively, compared to state-of-the-art implementation. Moreover, our algorithms require less stack space than the others.

Shifting Capsule Networks from the Cloud to the Deep Edge

Capsule networks (CapsNets) are an emerging trend in image processing. In contrast to a convolutional neural network, CapsNets are not vulnerable to object deformation, as the relative spatial information of the objects is preserved across the network. However, their complexity is mainly related to the capsule structure and the dynamic routing mechanism, which makes it almost unreasonable to deploy a CapsNet, in its original form, in a resource-constrained device powered by a small microcontroller (MCU). In an era where intelligence is rapidly shifting from the cloud to the edge, this high complexity imposes serious challenges to the adoption of CapsNets at the very edge. To tackle this issue, we present an API for the execution of quantized CapsNets in Arm Cortex-M and RISC-V MCUs. Our software kernels extend the Arm CMSIS-NN and RISC-V PULP-NN to support capsule operations with 8-bit integers as operands. Along with it, we propose a framework to perform post-training quantization of a CapsNet. Results show a reduction in memory footprint of almost 75%, with accuracy loss ranging from 0.07% to 0.18%. In terms of throughput, our Arm Cortex-M API enables the execution of primary capsule and capsule layers with medium-sized kernels in just 119.94 and 90.60 ms, respectively (STM32H755ZIT6U, Cortex-M7 @ 480 MHz). For the GAP-8 SoC (RISC-V RV32IMCXpulp @ 170 MHz), the latency drops to 7.02 and 38.03 ms, respectively.

FASLR: Function-Based ASLR via TrustZone-M and MPU for Resource-Constrained IoT Systems

The address space layout randomization (ASLR) has been widely deployed on modern operating systems against code reuse attacks (CRAs), such as return-oriented programming (ROP) and jump-oriented programming (JOP). However, porting ASLR to resource-constrained IoT devices is a great challenge due to the limited memory space for randomization. We propose a function-based ASLR scheme (fASLR) for IoT runtime security utilizing the ARM TrustZone-M technology and the memory protection unit (MPU) supported by ARM Cortex-M processors. fASLR loads a function from the flash and randomizes its base address in a randomization region in RAM when the function is being called. We design novel mechanisms on cleaning up finished functions from the RAM and memory addressing to tackle the complexity of function relocation and randomization. Optimizations are applied to effectively reduce overhead introduced by runtime memory management. We also formally prove that user applications will run correctly with fASLR enabled. Compared with the related work, a prominent advantage of fASLR is that fASLR can run an application even if the application code cannot be completely loaded into RAM for execution. We test fASLR with 21 applications. The experimental results show that fASLR achieves a high randomization entropy and incurs a runtime overhead of less than 10%.

Electrodeless Heart and Respiratory Rate Estimation during Sleep Using a Single Fabric Band and Event-Based Edge Processing.

Heart rate (HR) and respiratory rate (RR) are two vital parameters of the body medically used for diagnosing short/long-term illness. Out-of-the-body, non-skin-contact HR/RR measurement remains a challenge due to imprecise readings. “Invisible” wearables integrated into day-to-day garments have the potential to produce precise readings with a comfortable user experience. Sleep studies and patient monitoring benefit from “Invisibles” due to longer wearability without significant discomfort. This paper suggests a novel method to reduce the footprint of sleep monitoring devices. We use a single silver-coated nylon fabric band integrated into a substrate of a standard cotton/nylon garment as a resistive elastomer sensor to measure air and blood volume change across the chest. We introduce a novel event-based architecture to process data at the edge device and describe two algorithms to calculate real-time HR/RR on ARM Cortex-M3 and Cortex-M4F microcontrollers. RR estimations show a sensitivity of 99.03% and a precision of 99.03% for identifying individual respiratory peaks. The two algorithms used for HR calculation show a mean absolute error of 0.81 ± 0.97 and beats/min compared with a gold standard ECG-based HR. The event-based algorithm converts the respiratory/pulse waveform into instantaneous events, therefore reducing the data size by 40–140 times and requiring 33% less power to process and transfer data. Furthermore, we show that events hold enough information to reconstruct the original waveform, retaining pulse and respiratory activity. We suggest fabric sensors and event-based algorithms would drastically reduce the device footprint and increase the performance for HR/RR estimations during sleep studies, providing a better user experience.

Study on the Application of Microcontroller-Based GPS Sensors on Floater Gliders to Reach the Specified Destination

The purpose of the study is to determine the performance of the control system of the floater glider to a predetermined location. The method used was a combination between software simulation and an experimental free-running test. The Floater control system is equipped with GPS as input and output sensors to determine coordinates or waypoints. The microcontroller mounted was Pixhawk 2.4.8 based on ARM cortex M4 – 32 bits. The floater was driven by two Brushless DC motors and servo motors to drive the Z-Peller steering to the desired trajectory. The floater system applies the default application software from Pixhawk, namely mission planner to plan and also monitor the actual trajectory. To have a proper procedure for testing the designed control system, the three stages of the test were conducted, firstly numerical tuning test using step function on MATLAB simulation, then trajectory simulation test of waypoint using mission planner, and finally the field test in the ILH pond. From the three stages of the test, it was found that the selection of PID gain values Kp = 0.2, Ki = 0.3, and Kd = 0.02, indicating the performance of the floater glider control system to the planned location has a good fit between the trajectory simulation results and the waypoint testing in the pond. These results can be used as a reference in conducting further research so that the navigation accuracy of the control system will be improved.

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing

This article presents the design, implementation methodology, and validation of a multi-bit flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single-event transients (SETs) caused by radiation strikes. The proposed solution also has embedded timing pre-error sensing capability, which enables closed-loop integration of digital systems to work at optimal operating point (OPP) without any fail. It allows efficient real-time dynamic voltage frequency scaling (DVFS) implementation in the digital system. It helps detect aging-related and total ionizing dose (TID)-induced timing degradation in digital circuits. It can be implemented with any standard digital cell library (non-rad-hard), thereby providing a cost-effective solution for rad-hard applications. The design is implemented in ST BCD 90-nm technology in multiple configurations of bit sizes. A digital system based on ARM cortex M4 microprocessor has also been implemented with the proposed FF and put on silicon for testing to validate various capabilities of the proposed design. The results are presented based on simulations, electrical characterization, and radiation tests.

Roulette: A Diverse Family of Feasible Fault Attacks on Masked Kyber

At Indocrypt 2021, Hermelink, Pessl, and Pöppelmann presented a fault attack against Kyber in which a system of linear inequalities over the private key is generated and solved. The attack requires a laser and is, understandably, demonstrated with simulations—not actual equipment. We facilitate and diversify the attack in four ways, thereby admitting cheaper and more forgiving fault-injection setups. Firstly, the attack surface is enlarged: originally, the two input operands of the ciphertext comparison are covered, and we additionally cover re-encryption modules such as binomial sampling and butterflies in the last layer of the inverse numbertheoretic transform (INTT). This extra surface also allows an attacker to bypass the custom countermeasure that was proposed in the Indocrypt paper. Secondly, the fault model is relaxed: originally, precise bit flips are required, and we additionally support set-to-0 faults, random faults, arbitrary bit flips, and instruction skips. Thirdly, masking and blinding methods that randomize intermediate variables kindly help our attack, whereas the IndoCrypt attack is like most other fault attacks either hindered or unaltered by countermeasures against passive side-channel analysis (SCA). Randomization helps because we randomly fault intermediate prime-field elements until a desired set of values is hit. If these prime-field elements are represented on a circle, which is a common visualization, our attack is analogous to spinning a roulette wheel until the ball lands in a desired set of pockets. Hence, the nickname. Fourthly, we accelerate and improve the error tolerance of solving the system of linear inequalities: run times of roughly 100 minutes are reduced to roughly one minute, and inequality error rates of roughly 1% are relaxed to roughly 25%. Benefiting from the four advances above, we use a reasonably priced ChipWhisperer® board to break a masked implementation of Kyber running on an ARM Cortex-M4 through clock glitching.

A Key-Recovery Side-Channel Attack on Classic McEliece Implementations

In this paper, we propose the first key-recovery side-channel attack on Classic McEliece, a KEM finalist in the NIST Post-quantum Cryptography Standardization Project. Our novel idea is to design an attack algorithm where we submit special ciphertexts to the decryption oracle that correspond to cases of single errors. Decoding of such ciphertexts involves only a single entry in a large secret permutation, which is part of the secret key. Through an identified leakage in the additive FFT step used to evaluate the error locator polynomial, a single entry of the secret permutation can be determined. Iterating this for other entries leads to full secret key recovery. The attack is described using power analysis both on the FPGA reference implementation and a software implementation running on an ARM Cortex-M4. We use a machine-learning-based classification algorithm to determine the error locator polynomial from a single trace. The attack is fully implemented and evaluated in the Chipwhisperer framework and is successful in practice. For the smallest parameter set, it is using about 300 traces for partial key recovery and less than 800 traces for full key recovery, in the FPGA case. A similar number of traces are required for a successful attack on the ARM software implementation.

Verified NTT Multiplications for NISTPQC KEM Lattice Finalists: Kyber, SABER, and NTRU

Postquantum cryptography requires a different set of arithmetic routines from traditional public-key cryptography such as elliptic curves. In particular, in each of the lattice-based NISTPQC Key Establishment finalists, every state-ofthe-art optimized implementation for lattice-based schemes still in the NISTPQC round 3 currently uses a different complex multiplication based on the Number Theoretic Transform. We verify the NTT-based multiplications used in NTRU, Kyber, and SABER for both the AVX2 implementation for Intel CPUs and for the pqm4 implementation for the ARM Cortex M4 using the tool CryptoLine. e extended CryptoLine and as a result are able to verify that in six instances multiplications are correct including range properties.We demonstrate the feasibility for a programmer to verify his or her high-speed assembly code for PQC, as well as to verify someone else’s high-speed PQC software in assembly code, with some cooperation from the programmer.

Energy efficient mixed task handling on real-time embedded systems using FreeRTOS

With the increased use of embedded devices in Industrial electronics, like relays, battery life has gained more and more attention. Modern processors can use Dynamic Voltage Frequency Scaling (DVFS) techniques for energy reduction and temperature control. However, DVFS is not well supported by systems running with Real-Time operating systems like FreeRTOS, which is a widely used real-time operation system (RTOS) in the industry. Furthermore, energy-efficient DVFS techniques for Mixed Tasksets (including periodic and aperiodic tasks) are hardly investigated. This paper extends the classic well-known DVFS technique Cycle Conserving algorithm to handle Mixed Taskset (CCMT algorithm) and implements it on a real-time embedded platform powered by FreeRTOS. We describe our experience implementing CCMT on a real platform with limited DVFS and corresponding scheduler support. Results show that we can successfully apply CCMT to handle aperiodic requests while meeting the deadlines of the periodic tasks and saving energy on the FreeRTOS platform. The algorithm is tested on an ARM Cortex-M7 processor integrated with frequency scaling and power management. Over 5% to 10% energy savings can be achieved for a standard real-time scheduling mechanism without penalty in application throughput.