ARM Cortex Research Articles

Dependability Measurement with Soft Error Caused Exceptions on the Arm Cortex-A9 CPU

Dependability Measurement with Soft Error Caused Exceptions on the Arm Cortex-A9 CPU

A Fast Fixed-Point Logarithmic Functions Based on ARM Microprocessor

The fixed-point mathematical library refers to a highly optimized collection of high-precision mathematical functions primarily used for fast and high-precision real-time calculations. It can execute equivalent code written in the C language with floating-point format faster, while maintaining considerable accuracy. Current mainstream fixed-point mathematical libraries face issues such as being non-open source, having unknown models, incomplete basic mathematical operation functions, and insufficient precision. Therefore, designing an open-source, fast, more optimized, and high-precision fixed-point mathematical library will have a groundbreaking impact. It can not only play a crucial role in industrial control algorithms but also eliminate the dependency of domestic fixed-point MCUs on foreign library functions. This paper conducts research on fixed-point arithmetic for logarithmic functions, designs, and improves the implementation of fast logarithmic functions.Taking Q12 as an example, Simulation experiments and MCU experiments show that, in the Q12 format, the highest precision that can be represented by a 32-bit fixed-point number is 0.000244141. From the test results, it can be observed that for 98.15% of the test data, the computational errors of the two mathematical libraries are both smaller than the highest precision value. Both two logarithmic function computations can maintain good computational accuracy within the ARM microprocessor. In terms of computational speeds, the average computation cycle of the fixed-point logarithmic function designed in this paper is reduced by 31.88% compared to the counterpart. This substantial improvement in computational speed, while ensuring computational accuracy, enhances the performance of fixed-point logarithmic operations based on ARM microprocessors.

Improving Code Compression for Arm Cortex M Microcontrollers Using Pre- Filtering

For last decades code size is no longer a concern except small embedded systems. ARM Cortex M is a typical microcontroller architecture of such systems. A simple yet effective approach based on pre- filtering Thumb2 binary code is proposed to improve code compression by the general purpose Deflate algorithm. It transforms BL (branch and link) instructions pointing to the same effective address before compression, and restores original opcodes after decompression. Tests performed on real-life embedded software show that the proposed algorithm improves code compression by approximately 3 %.

Integration of STM32 Microcontroller with Arm Cortex Architecture into the 8-Bit Measurement Circuit Customized for Real-Time Data Acquisition on Propeller Shaft to Increase Data Speed and Accuracy

Propeller shafts transmit torque and high-speed rotational movement from the engine to related equipment. Expected propeller shaft functions are calculated and designed by using an analytical and numerical approaches. The verification tests are significant in that they provide feedback to the design and development processes. Therefore, acquiring accurate data from power transmission equipment is becoming even more important. This paper focuses on the study of circuit boards customized for use in the validation tests of the propeller shafts. It should be noted that these measurement circuits were integrated on the propeller shafts. These measurement circuits were used to acquire data such as torque, temperature, etc. in real time. Especially with instantaneous signals such as torque, data loss can occur due to low microcontroller resolution. Therefore, it was aimed to develop to the microcontroller to 32-bit resolution from 8-bit resolution to increase data speed and accuracy. As the first step, an INA125P operational amplifier was installed to amplify the low voltage values gathered from the gages and the sensors. The gain value of the amplifier was calculated in order to provide the highest data resolution and sensitivity. And then, ADS1115 analog to digital converter circuit with a rate of 860 samples per second and 16-bit resolution was used to interpret the analog data. A low pass filter was installed to remove noise from the output signal. Embedded code was also locally developed for the hardware installed. The system was calibrated on a validated test rig. Real-time torque and temperature data were acquired from the propeller shaft. It is observed that compared to the previous 8-bit system, the data accuracy and integrity from the new 32-bit board has increased by a factor of 5 to 100 Hz. The collected data was found to be 99.4% compatible with the validated test rig data.

Description, Implementation and Performance/Security Analysis of ASCON128

The aim of the report is to introduce detailed description of the functioning of and to provide an efficient implementation (using bit-sliced implementation of S-Box) in C of encryption, decryption and authentication of the lightweight authenticated encryption algorithm ASCON 128 (sponge based SPN network based on Keccak like operations) as per the v 1.2 submitted to NIST. This is achieved using a sponge construction by setting up initialization state and performing 12 rounds of permutations, XORing consecutively the plaintext blocks (encryption) or ciphertext blocks (decryption) with first 64 bits of the state (after 6 rounds of sponge permutations) and after all consecutive operations on ciphertext/plaintext blocks, XORing the last 128 bits of the resultant state with the secret Key (after 12 rounds of final permutation operations) to produce/re-create the tag. Discussions on Key Features, Performance Analysis (comparison of ASCON 128 v/s AES 128 in GCM mode on our own PC), Performance Comparisons with other NIST lightweight cryptography contest finalists on ARM Cortex M3, and discussions on the Security Analysis (side channel attacks: fault injection and power analysis) of ASCON are included in this report.

POWER PROCESSING AND CONTROL UNIT OF THE EECTRIC PROPULSION SYSTEM

Abstract. The report presents the results of the development of the PPU-500, which is part of the SPS-500 electric propulsion system based on the ST-40 Hall thruster. PPU-500 contains all power supplies necessary for the operation of the propulsion system: discharge; electromagnet; cathode heater and keeper; power supplies for valves and heaters of the storage and feeding working substance, as well as a standby power supply that ensures the standby mode of PPU operation.The converter of the discharge power supply is built using a bridge topology with a phase-shifted output power control circuit. The remaining power supplies are built according to the topology of a step-down synchronous converter with current or voltage stabilization. The discharge power supply is a controlled power supply. The power supplies for the cathode heater and electromagnet current sources are. The accuracy of power supplies output parameters in not worse than 1.5%. The valves of the feeding system are controlled in order to stabilize the pressure in the receiver by periodically turning on/turning off the high- and low-pressure valves. For control the valves, signals taken from pressure sensors installed in the receiver are used. The PPU control unit ensures an accuracy of maintaining pressure in the receiver no worse than 2.5%. The control unit of the PPU is built using a microcontroller with an ARM core. It implements the functions of monitoring the condition of the program, restoring the program firmware if an integrity violation is detected, and the ability to remotely flash a new version. To communicate the SPS-500 with the on-board control system, a galvanically isolated CAN interface is used. It can be also the RS485/RS42 interface.During operation of the propulsion system, operating parameters are measured using multi-channel ADCs and DACs. The obtained data, on the one hand, is used to assess the current state of the propulsion system and control Hall thruster operating modes. On the other hand, they are transmitted as telemetry signals reflecting the current state of the SPS-500, operating mode and emerging emergency conditions of the equipment. PPU is possible to alternately control two thrusters. Solid-state switches are used to switch the corresponding power sources.Testing of the PPU-500 as part of the SPS-500 propulsion system with the ST-40 Hall thruster and a flight prototype of the working substance feeding system confirmed the technical solutions adopted. The operating efficiency of PPU-500 for the nominal operating mode of the propulsion system is 94%.

A Secure Key Expansion Algorithm for Present

The efficiency of a cryptographic algorithm in terms of security depends on the resistance against cryptanalytic attacks. Besides the complexity of the encryption algorithm, the key plays an essential role in the security against cryptanalytic attacks. The strength and complexity of the encryption algorithm do not suffice and serve the fundamental purpose of security if the key is compromised at any stage. So, apart from the cryptanalytically robust encryption algorithm, a strong key schedule is also essential to thwart possible attacks against a particular algorithm. PRESENT, a lightweight encryption technique with a simple design, is resistant to linear and differential attacks but has a weak key schedule and is susceptible to cryptanalytic attacks. This paper proposes an efficient key scheduling algorithm for PRESENT lightweight encryption technique resistant against cryptanalytic attacks. Statistical tests examine the proposed key schedule’s cryptographic strength on the properties of subkeys produced in the key generation mechanism. The tests prove the efficiency of the proposed key schedule in terms of cryptanalytic attacks. Implementation and comparison of the efficacy of the proposed key schedule in terms of security and implementation costs are illustrated with the PRESENT-80 key schedule and the PRESENT-128 key schedule. The key scheduling algorithm is implemented on the ARM Cortex M3-based NXP LPC 1857 and 1768 hardware development platforms. The results indicate the efficiency of the proposed algorithm in terms of security, performance, and power consumption across the two hardware platforms.

Message Authentication and Provenance Verification for Industrial Control Systems

Successful attacks against industrial control systems (ICSs) often exploit insufficient checking mechanisms. While firewalls, intrusion detection systems, and similar appliances introduce essential checks, their efficacy depends on the attackers’ ability to bypass such middleboxes. We propose a provenance solution to enable the verification of an end-to-end message delivery path and the actions performed on a message. Fast and flexible provenance verification (F2-Pro) provides cryptographically verifiable evidence that a message has originated from a legitimate source and gone through the necessary checks before reaching its destination. F2-Prorelies on lightweight cryptographic primitives and flexibly supports various communication settings and protocols encountered in ICS thanks to its transparent, bump-in-the-wire design. We provide formal definitions and cryptographically prove F2-Pro’s security. For human interaction with ICS via a field service device, F2-Profeatures a multi-factor authentication mechanism that starts the provenance chain from a human user issuing commands. We compatibility tested F2-Proon a smart power grid testbed and reported a sub-millisecond latency overhead per communication hop using a modest ARM Cortex-A15 processor.

Design and implementation of low-power, high-speed, reliable and secured Hardware Accelerator using 28 nm technology for biomedical devices

This paper implements a Hardware Accelerator (HA) for Wireless Body Sensor Networks (WBSNs) using 28 nm technology on Zynq system-on-a-chip (SOC) using Vivado and VITIS high-level synthesis tool. The Vitis integrated development environment (IDE) is a software-only development environment that Integrates with other Xilinx tools. The Zynq® SoC combines a state-of-the-art processor system (PS) and programmable logic (PL) into a single cohesive device. WBSNs contain different processing techniques like predictor, compressor, encryption encoder, and Error Control Coding (ECC) before transmission. These techniques are implemented and validated using the Xilinx® Software Development Kit (SDK) tool along with the PYNQ Z2 board having Zynq SOC respectively. Similarly, the processing techniques are implemented on PS block as HA. The results of the work show the data collection and processing through the dual-core ARM Cortex A9 processor of the board. The purpose of the work is to calculate the time required to process the bio-signals through the controller solely and using HA. The proposed work, mainly WBSN using HA shows an improvement of 81% in the speed compared with existing methods. Further, results of the synthesis and implementation strategy show improvement in power and area of HA with WBSN.

An acoustic echo canceller optimized for hands-free speech telecommunication in large vehicle cabins

Acoustic echo cancelation (AEC) is a system identification problem that has been addressed by various techniques and most commonly by normalized least mean square (NLMS) adaptive algorithms. However, performing a successful AEC in large commercial vehicles has proved complicated due to the size and challenging variations in the acoustic characteristics of their cabins. Here, we present a wideband fully linear time domain NLMS algorithm for AEC that is enhanced by a statistical double-talk detector (DTD) and a voice activity detector (VAD). The proposed solution was tested in four main Volvo truck models, with various cabin geometries, using standard Swedish hearing-in-noise (HINT) sentences in the presence and absence of engine noise. The results show that the proposed solution achieves a high echo return loss enhancement (ERLE) of at least 25 dB with a fast convergence time, fulfilling ITU G.168 requirements. The presented solution was particularly developed to provide a practical compromise between accuracy and computational cost to allow its real-time implementation on commercial digital signal processors (DSPs). A real-time implementation of the solution was coded in C on an ARM Cortex M-7 DSP. The algorithmic latency was measured at less than 26 ms for processing each 50-ms buffer indicating the computational feasibility of the proposed solution for real-time implementation on common DSPs and embedded systems with limited computational and memory resources. MATLAB source codes and related audio files are made available online for reference and further development.

AIoT-Driven Edge Computing for Rural Small-Scale Poultry Farming: Smart Environmental Monitoring and Anomaly Detection for Enhanced Productivity

The growing demand for chicken production has emphasized the importance of maintaining optimal conditions to improve quality and productivity.The integration of Artificial Intelligence (AI) and the Internet of Things(IoT) is recommended for the efficient management of the farm's environment. A potential solution is presented in this paper, utilizing IoT-based sensor nodes with ARM Cortex M3 - LPC 1769 and LORA technology to monitor chicken farms across diverse regions.The proposed solution incorporates a low-cost edge computing server-Jetson Nano device equipped with a machine learning model to categorize and monitor live environmental conditions in poultry farms. Real-time data from various branches is collected and analyzed using machine learning classification techniques including logistic regression, K nearest neighbors, and support vector machines.The performance of these algorithms is compared to identify the most effective approach. Upon evaluation, the K nearest neighbors emerges as the superior performer, achieving an impressive accuracy of 99.72% and an execution duration of 0.087 seconds on the Jetson Nano edge computing device. This cost-effective technology is tailored for small businesses in regions where farmers can gain valuable insights from data-driven decisions and closely monitor their operations. By incorporating AIoT into farm management, the challenges faced by small-scale poultry farming can be addressed, empowering farmers with enlightened techniques to improve overall productivity and quality.

Dy-MAC: Implementation of dynamic MAC stack for IEEE 802.15.4e-TSCH

This paper presents the lessons learnt in the implementation of IEEE 802.15.4e-Time Slotted Channel Hopping (TSCH) Medium Access Control (MAC) protocol on commercially available hardware. Our MAC Application programming Interface (API) called the Dy-MAC is agnostic to the PHY layer and is coded on a ARM cortex M4. MAC functions such as TDMA, FDMA, frame counter, channel access, synchronization and PAN formation are abstracted as part of this API. Dy-MAC is demonstrated for 2.4GHz with O-QPSK modulation and 868MHz with SUN FSK modulation. Furthermore, the API supports star, mesh and tree network to provide flexible topologies in factory environment. Our experiments show that for a 76 byte payload, the TSCH Dy-MAC provides ∼99% packet delivery ratio (PDR) for 26ms timeslot with SUN FSK PHY and ∼97% PDR for 10ms timeslot with O-QPSK PHY. To maintain synchronization over the entire network, we implemented algorithms to successfully communicate between fast and slow nodes. Resilience to interference and range with packet delivery ratio is evaluated. We consolidate our implementation in terms of 10 lessons that were learnt in building the Dy-MAC protocol.

Loop Aborts Strike Back: Defeating Fault Countermeasures in Lattice Signatures with ILP

At SAC 2016, Espitau et al. presented a loop-abort fault attack against lattice-based signature schemes following the Fiat–Shamir with aborts paradigm. Their attack recovered the signing key by injecting faults in the sampling of the commitment vector (also called masking vector) y, leaving its coefficients at their initial zero value. As possible countermeasures, they proposed to carry out the sampling of the coefficients of y in shuffled order, or to ensure that the masking polynomials in y are not of low degree. In this paper, we show that both of these countermeasures are insufficient. We demonstrate a new loop-abort fault injection attack against Fiat–Shamir with aborts lattice-based signatures that can recover the secret key from faulty signatures even when the proposed countermeasures are implemented. The key idea of our attack is that faulted signatures give rise to a noisy linear system of equations, which can be solved using integer linear programming. We present an integer linear program that recovers the secret key efficiently in practice, and validate the efficacy of our attack by conducting a practical end-to-end attack against a shuffled version of the Dilithium reference implementation, mounted on an ARM Cortex M4. We achieve a full (equivalent) key recovery in under 3 minutes total execution time (including signature generation), using only 5 faulted signatures. In addition, we conduct extensive theoretical simulations of the attack against Dilithium. We find that our method can achieve key recovery in under 5 minutes given a (sufficiently large) set of signatures where just one of the coefficients of y is zeroed out (or left at its initial value of zero). Furthermore, we find that our attack works against all security levels of Dilithium. Our attack shows that protecting Fiat–Shamir with aborts lattice-based signatures against fault injection attacks cannot be achieved using the simple countermeasures proposed by Espitau et al. and likely requires significantly more expensive countermeasures.

Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography

Hybrid key encapsulation is in the process of becoming the de-facto standard for integration of post-quantum cryptography (PQC). Supporting two cryptographic primitives is a challenging task for constrained embedded systems. Both contemporary cryptography based on elliptic curves or RSA and PQC based on lattices require costly multiplications. Recent works have shown how to implement lattice-based cryptography on big-integer coprocessors. We propose a novel hardware design that natively supports the multiplication of polynomials and big integers, integrate it into a RISC-V core, and extend the RISC-V ISA accordingly. We provide an implementation of Saber and X25519 to demonstrate that both lattice- and elliptic-curve-based cryptography benefits from our extension. Our implementation requires only intermediate logic overhead, while significantly outperforming optimized ARM Cortex M4 implementations, other hardware/software codesigns, and designs that rely on contemporary accelerators.

Design of New LED Curtain Wall Controller and Its Effect in Architectural Decoration

In recent years, LED with high brightness or ultra-high brightness has appeared. Because of its low production cost, it has been widely used. Compared with other display media, LED has the advantages of rich display content, wide dynamic range, vivid picture, no pollution, long life, etc., so it is used in building curtain wall facade decoration. This research designs LED curtain wall control system, the use of SD600 chip dimming control of LED, the use of absorbing current mode LED drive, further design of single SD600 chip application circuit, multi-SD600 chip application circuit. LED curtain wall display text need to design the corresponding graphic processing hardware, the hardware is composed of ARM microprocessor LPC2210 and its related peripheral circuits. The core chip of the LPC2210 processor chip needs 1.8 V working voltage, and the I/O interface voltage is 3.3 V, so it is necessary to design the corresponding power circuit; The system clock is adjusted through the internal PLL circuit to make the system run faster and design its crystal oscillator circuit; The power monitoring chip CAT1025JI-30 is adopted to build reset circuit, 20-pin interface type JTAG interface circuit; It is considered that the UARTO interface can’t be directly connected with the RS232 interface of PC, the MAX3232 chip is introduced for level conversion, and the serial interface circuit based on LPC2210 is designed. In the experiment, the new technology is used for outdoor lighting LED curtain wall construction, and the development tool uses the ADS1.2 provided by ARM company. The μC/OS-II embedded operating system is introduced to control the graphic processing hardware resources, reading the file from the SD card, and writing the text file and BMP file into the three-dimensional array, the corresponding text and pattern effect are displayed in the LED curtain wall.

A Lightweight Mitigation Technique for Resource- Constrained Devices Executing DNN Inference Models Under Neutron Radiation

Deep neural network (DNN) models are being deployed in safety-critical embedded devices for object identification, recognition, and even trajectory prediction. Optimised versions of such models, in particular the convolutional ones, are becoming increasingly common in resource-constrained edge-computing devices (e.g., sensors, drones), which typically rely on reduced memory footprint, low power budget and low-performance microprocessors. DNN models are prone to radiation-induced soft errors, and tackling their occurrence in resource-constrained devices is a mandatory and substantial challenge. While traditional replication-based soft error mitigation techniques will likely account for a reasonable performance penalty, hardware solutions are even more costly. To undertake this almost contradictory challenge, this work evaluates the efficiency of a lightweight software-based mitigation technique, called Register Allocation Technique (RAT), when applied to a convolutional neural network (CNN) model running on two commercial Arm microprocessors (i.e., Cortex-M4 and M7) under the effects of neutron radiation. Gathered results obtained from two neutron radiation campaigns suggest that RAT can reduce the number of critical faults in the CNN model running on both Arm Cortex-M microprocessors. Results also suggest that the SDC FIT rate of the RAT-hardened CNN model can be reduced in up to 83% with a runtime overhead of 32%.

Interpretable Rule Mining for Real-Time ECG Anomaly Detection in IoT Edge Sensors

Electrocardiogram (ECG) analysis is widely used in the diagnosis of cardiovascular diseases. This paper proposes an explainable rule-mining strategy for prioritizing abnormal class detection in ECG data. The proposed method utilizes a biased-trained Artificial Neural Network (ANN) with input features derived from an ECG beat sequence and formulates a set of rules at each node of an on-demand tree-like search algorithm. The rule base at each node is derived from a linear combination of the most impactful features identified using gradient analysis in an ANN. The final derived model is an explainable rule-based system that detects abnormal heartbeats based on statistical and morphological features from ECG. The model achieves the target sensitivity, and accuracy with a low run-time complexity through a comprehensive offline rule mining process and is trained using the MIT-BIH Arrhythmia Database. The system achieves an accuracy of 93% with only nine nodes and a test sensitivity of 90% and 80% respectively for VEB and SVEB beat types, when tested on previously unseen ECG data from the INCART database. The model performance and complexity can be easily adjusted based on the real-time resource constraints of a wearable sensor. The model was deployed on an ARM Cortex M4-based embedded device and is shown to achieve a >50% reduction in sensor power consumption when only abnormal beats are wirelessly transmitted. i.e RF transmission is gated using the model output and transmission is disabled when the subject’s ECG is normal. The proposed technique is highly suited for healthcare applications because of its explainability, lower complexity, and real-time flexibility when deployed in the Internet of Things (IoT) enabled wearable edge sensors.

IoT-Enabled System for Detection, Monitoring, and Tracking of Nuclear Materials

A low-cost embedded system for high-energy radiation detection applications was developed for national security proposes, mainly to detect nuclear material and send the detection event to the cloud in real time with tracking capabilities. The proof of concept was built with state-of-the-art electronics such as an adequate Si-based photodetector, a trans-impedance amplifier, an ARM Cortex M4 microcontroller with sufficient ADC capture capabilities, an ESP8266 Internet of Things (IoT) module, an optimized Message Queuing Telemetry Transport (MQTT) protocol, a MySQL data base, and a Python handler program. The system is able to detect alfa particles and send the nuclear detection events to the CloudMQTT servers. Moreover, the detection message records the date and time of the ionization event for the tracking application, and due to a particular MQTT-optimized protocol the message is sent with low latency. Furthermore, the designed system was validated with a standard radiation instrumentation preamplifier 109A system from ORTEC company, and more than one node was demonstrated with an internet connection employing a 20,000 bits/s CloudMQTT plan. Therefore, the design can be escalated to produce a robust big data multisensor network.

Pedestrian Tracking in UAV Images With Kalman Filter Motion Estimator and Correlation Filter

Visual object tracking is one of the significant parts of systems varying from autonomous driving to drone-based surveillance/tracking. Discriminative correlation filter (DCF) based trackers have proved their prominence in the past few years. These utilize visual information present in images for monitoring. This work uses the Kalman Filter (KF) to derive a motion estimation model. It combines it with two DCF-based trackers, namely Kernelized Correlation Filter (KCF) and Discriminative Correlation Filter with Channel and Spatial Reliability (CSRDCF) for pedestrian tracking. Camera motion-compensated versions of the trackers are also presented. The performance of the proposed methodology is presented in terms of Success Rate (SR) and Precision (P). Real-time power consumption, memory occupancy, and speed of trackers on the Jetson Nano (ARM Cortex-A57, 4 GB RAM) board have been presented.

High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium

CRYSTALS-Dilithium is a lattice-based post-quantum digital signature scheme that is resistant to attacks by quantum computers and has been selected to be standardized in the NIST post-quantum cryptography (PQC) standardization process. However, the speed performance and design flexibility of the Dilithium still need to be evaluated. This article presents a high-performance software/hardware co-design of CRYSTALS-Dilithium based on the NIST PQC round-3 parameters. High-speed pipelined hardware modules for NTT/INTT, point-wise multiplication/addition, and for SHAKE are included in the design to accelerate the time-consuming operations in Dilithium. All hardware modules are parameterized, thus allowing full support of runtime configuration to increase versatility. Moreover, the proposed software/hardware architecture and tight operating workflows reduce the data transmission overhead between the processor and other hardware modules. The hardware accelerator is implemented with a reconfigurable logic on FPGA and is integrated with the high-performance ARM Cortex-A9 processor in the Xilinx Zynq Architecture. We measure the performance of the software/hardware system for Dilithium in NIST security levels 2, 3, and 5. Compared to pure software implementations, we achieve 8.7–12.5 times speedup in Key generation, 6.3–7.3 times speedup in Sign, and 9.1–12.2 times speedup in Verify operations.